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Message-ID: <20250526162954.2467894-1-ciprianmarian.costea@oss.nxp.com>
Date: Mon, 26 May 2025 19:29:53 +0300
From: Ciprian Costea <ciprianmarian.costea@....nxp.com>
To: Shawn Guo <shawnguo@...nel.org>
Cc: linux-kernel@...r.kernel.org,
Christophe Lizzi <clizzi@...hat.com>,
Alberto Ruiz <aruizrui@...hat.com>,
Enric Balletbo <eballetb@...hat.com>,
Eric Chanudet <echanude@...hat.com>,
imx@...ts.linux.dev,
Ciprian Marian Costea <ciprianmarian.costea@....nxp.com>
Subject: [PATCH] arm64: dts: s32g: add RTC node
From: Ciprian Marian Costea <ciprianmarian.costea@....nxp.com>
The RTC module on S32G2/S32G3 based SoCs is used as a wakeup source from
system suspend.
Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@....nxp.com>
---
arch/arm64/boot/dts/freescale/s32g2.dtsi | 8 ++++++++
arch/arm64/boot/dts/freescale/s32g3.dtsi | 9 +++++++++
2 files changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index fa054bfe7d5c..39d12422e3f3 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -114,6 +114,14 @@ soc@0 {
#size-cells = <1>;
ranges = <0 0 0 0x80000000>;
+ rtc0: rtc@...60000 {
+ compatible = "nxp,s32g2-rtc";
+ reg = <0x40060000 0x1000>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 54>, <&clks 55>;
+ clock-names = "ipg", "source0";
+ };
+
pinctrl: pinctrl@...9c240 {
compatible = "nxp,s32g2-siul2-pinctrl";
/* MSCR0-MSCR101 registers on siul2_0 */
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index b4226a9143c8..e71b80e048dc 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -171,6 +171,15 @@ soc@0 {
#size-cells = <1>;
ranges = <0 0 0 0x80000000>;
+ rtc0: rtc@...60000 {
+ compatible = "nxp,s32g3-rtc",
+ "nxp,s32g2-rtc";
+ reg = <0x40060000 0x1000>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks 54>, <&clks 55>;
+ clock-names = "ipg", "source0";
+ };
+
pinctrl: pinctrl@...9c240 {
compatible = "nxp,s32g2-siul2-pinctrl";
/* MSCR0-MSCR101 registers on siul2_0 */
--
2.45.2
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