linux-kernel - Re: [PATCH v6 2/5] KVM: arm64: New function to determine hardware cache management support

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Message-ID: <20250527002516.GL61950@nvidia.com>
Date: Mon, 26 May 2025 21:25:16 -0300
From: Jason Gunthorpe <jgg@...dia.com>
To: ankita@...dia.com
Cc: maz@...nel.org, oliver.upton@...ux.dev, joey.gouly@....com,
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Subject: Re: [PATCH v6 2/5] KVM: arm64: New function to determine hardware
 cache management support

On Sat, May 24, 2025 at 01:39:40AM +0000, ankita@...dia.com wrote:
> From: Ankit Agrawal <ankita@...dia.com>

How about:

VM_PFNMAP VMA's are allowed to contain PTE's which point to physical
addresses that does not have a struct page and may not be in the kernel
direct map.

However ARM64 KVM relies on a simple conversion from physaddr to a
kernel virtual address when it does cache maintenance as the CMO
instructions work on virtual addresses. This simple approach does not
work for physical addresses from VM_PFNMAP since those addresses may
not have a kernel virtual address, or it may be difficult to find it.

Fortunately if the ARM64 CPU has two features, S2FWB and CACHE DIC,
then KVM no longer needs to do cache flushing and NOP's all the
CMOs. This has the effect of no longer requiring a KVA for addresses
mapped into the S2.

Add a new function, kvm_arch_supports_cacheable_pfnmap(), to report
this capability. From a core prespective it means the arch can accept
a cachable VM_PFNMAP as a memslot. From an ARM64 perspective it means
that no KVA is required.

> +/**
> + * kvm_arch_supports_cacheable_pfnmap() - Determine whether hardware
> + *      supports cache management.
> + *
> + * Return: True if FWB and DIC is supported.

I would elaborate some of the above commit message here so people
understand why FWB and DIC are connected to this.

Jason