lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <79903ad6-0228-41a3-b733-415cc43ec786@kernel.org>
Date: Tue, 27 May 2025 10:25:53 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Quentin Schulz <foss+kernel@...il.net>, Lee Jones <lee@...nel.org>,
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>, Heiko Stuebner <heiko@...ech.de>,
 Sebastian Reichel <sebastian.reichel@...labora.com>
Cc: Lukasz Czechowski <lukasz.czechowski@...umatec.com>,
 Daniel Semkowicz <dse@...umatec.com>, devicetree@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, linux-rockchip@...ts.infradead.org,
 linux-kernel@...r.kernel.org, Quentin Schulz <quentin.schulz@...rry.de>
Subject: Re: [PATCH 1/4] dt-bindings: mfd: rk806: allow to customize PMIC
 reset method

On 26/05/2025 19:05, Quentin Schulz wrote:
> From: Quentin Schulz <quentin.schulz@...rry.de>
> 
> The RK806 PMIC (and RK809, RK817; but those aren't handled here) has a
> bitfield for configuring the restart/reset behavior (which I assume
> Rockchip calls "function") whenever the PMIC is reset (at least by
> software; c.f. DEV_RST in the datasheet).
> 
> For RK806, the following values are possible for RST_FUN:
> 
> 0b00 means "restart PMU"
> 0b01 means "Reset all the power off reset registers, forcing
>             the state to switch to ACTIVE mode"
> 0b10 means "Reset all the power off reset registers, forcing
>             the state to switch to ACTIVE mode, and simultaneously
>             pull down the RESETB PIN for 5mS before releasing"
> 0b11 means the same as for 0b10 just above.
> 
> I don't believe this is suitable for a subsystem-generic property hence
> let's make it a vendor property called rockchip,rst-fun.
> 
> The first few sentences in the description of the property are
> voluntarily generic so they could be copied to the DT binding for
> RK809/RK817 whenever someone wants to implement that for those PMIC.
> 
> Signed-off-by: Quentin Schulz <quentin.schulz@...rry.de>
> ---
>  .../devicetree/bindings/mfd/rockchip,rk806.yaml    | 24 ++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml b/Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml
> index 3c2b06629b75ea94f90712470bf14ed7fc16d68d..0f931a6da93f7596eac89c5f0deb8ee3bd934c31 100644
> --- a/Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml
> +++ b/Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml
> @@ -31,6 +31,30 @@ properties:
>  
>    system-power-controller: true
>  
> +  rockchip,rst-fun:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [0, 1, 2, 3]
> +    description:
> +      RST_FUN value to set for the PMIC.
> +
> +      This is the value in the RST_FUN bitfield according to the
> +      datasheet. I.e. if RST_FUN is bits 6 and 7 and the desired value
> +      of RST_FUN is 1, this property needs to be set to 1 (and not 64,
> +      0x40, or BIT(6)).
> +
> +      The meaning of this value is specific to the PMIC and is
> +      explained in the datasheet.

And why would that be exactly board-level configuration? IOW, I expect
all boards to be reset in the same - correct and optimal - way. Looks
close to SW policy.

> +
> +      For RK806, the following applies
> +
> +      0b00 means "restart PMU"

Use decimal numbers.

> +      0b01 means "Reset all the power off reset registers, forcing
> +                  the state to switch to ACTIVE mode"
> +      0b10 means "Reset all the power off reset registers, forcing
> +                  the state to switch to ACTIVE mode, and simultaneously
> +                  pull down the RESETB PIN for 5mS before releasing"
> +      0b11 means the same as for 0b10 just above.
> +
>    vcc1-supply:
>      description:
>        The input supply for dcdc-reg1.
> 


Best regards,
Krzysztof

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ