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Message-ID: <20250527112403.1254122-1-claudiu.beznea.uj@bp.renesas.com>
Date: Tue, 27 May 2025 14:23:55 +0300
From: Claudiu <claudiu.beznea@...on.dev>
To: geert+renesas@...der.be,
mturquette@...libre.com,
sboyd@...nel.org,
robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
magnus.damm@...il.com
Cc: claudiu.beznea@...on.dev,
linux-renesas-soc@...r.kernel.org,
linux-clk@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Subject: [PATCH v3 0/8] clk: renesas: rzg2l-cpg: Drop PM domain abstraction for MSTOP
From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Hi,
Series drops the PM domain abstraction for MSTOP to comply with the
requirements received from the hardware team regarding the configuration
sequence b/w the MSTOP and CLKON bits of individual modules.
The initial MSTOP support for RZ/G3S was proposed here:
https://lore.kernel.org/all/20231120070024.4079344-4-claudiu.beznea.uj@bp.renesas.com/
There are no DT users of this abstraction yet.
Please share your thoughts.
Thank you,
Claudiu Beznea
Changes in v3:
- s/for_each_mstp_clk/for_each_mod_clock/g
- in rzg2l_mod_clock_module_set_state() update the register only of
!atomic_read() is true, in case the module is switched to normal
state
- move the update of shared_mstop_clks[] arrays before the priv->clks[]
is populated; with this the logic is simplified
- do not add clock to its own shared_mstop_clks[] array in case it
doesn't share the mstop with any other clock; kept it for case
where the mstop is shared with other clocks; the following is the
output of cat /sys/kernel/debug/mstop on RZ/G3S:
root@...rc-rzg3s:~# cat /sys/kernel/debug/mstop
MSTOP
clk -------------------------
clk_name cnt cnt off val shared
-------- ----- ----- ----- ------ ------
gic_gicclk 1 1 0xb60 0x0
ia55_clk 2 2 0xb70 0x0 ia55_pclk ia55_clk
ia55_pclk 2 2 0xb70 0x0 ia55_pclk ia55_clk
dmac_aclk 2 1 0xb80 0x0
dmac_pclk 1 1 0xb80 0x0
wdt0_pclk 0 0 0xb7c 0x1 wdt0_pclk wdt0_clk
wdt0_clk 0 0 0xb7c 0x1 wdt0_pclk wdt0_clk
sdhi0_imclk 1 4 0xb6c 0x0 sdhi0_imclk sdhi0_imclk2 sdhi0_clk_hs sdhi0_aclk
sdhi0_imclk2 2 4 0xb6c 0x0 sdhi0_imclk sdhi0_imclk2 sdhi0_clk_hs sdhi0_aclk
sdhi0_clk_hs 1 4 0xb6c 0x0 sdhi0_imclk sdhi0_imclk2 sdhi0_clk_hs sdhi0_aclk
sdhi0_aclk 1 4 0xb6c 0x0 sdhi0_imclk sdhi0_imclk2 sdhi0_clk_hs sdhi0_aclk
sdhi1_imclk 1 4 0xb6c 0x0 sdhi1_imclk sdhi1_imclk2 sdhi1_clk_hs sdhi1_aclk
sdhi1_imclk2 2 4 0xb6c 0x0 sdhi1_imclk sdhi1_imclk2 sdhi1_clk_hs sdhi1_aclk
sdhi1_clk_hs 1 4 0xb6c 0x0 sdhi1_imclk sdhi1_imclk2 sdhi1_clk_hs sdhi1_aclk
sdhi1_aclk 1 4 0xb6c 0x0 sdhi1_imclk sdhi1_imclk2 sdhi1_clk_hs sdhi1_aclk
sdhi2_imclk 0 0 0xb6c 0x800 sdhi2_imclk sdhi2_imclk2 sdhi2_clk_hs sdhi2_aclk
sdhi2_imclk2 0 0 0xb6c 0x800 sdhi2_imclk sdhi2_imclk2 sdhi2_clk_hs sdhi2_aclk
sdhi2_clk_hs 0 0 0xb6c 0x800 sdhi2_imclk sdhi2_imclk2 sdhi2_clk_hs sdhi2_aclk
sdhi2_aclk 0 0 0xb6c 0x800 sdhi2_imclk sdhi2_imclk2 sdhi2_clk_hs sdhi2_aclk
ssi0_pclk2 0 0 0xb64 0x400 ssi0_pclk2 ssi0_sfr
ssi0_sfr 0 0 0xb64 0x400 ssi0_pclk2 ssi0_sfr
ssi1_pclk2 0 0 0xb64 0x800 ssi1_pclk2 ssi1_sfr
ssi1_sfr 0 0 0xb64 0x800 ssi1_pclk2 ssi1_sfr
ssi2_pclk2 0 0 0xb64 0x1000 ssi2_pclk2 ssi2_sfr
ssi2_sfr 0 0 0xb64 0x1000 ssi2_pclk2 ssi2_sfr
ssi3_pclk2 0 0 0xb64 0x2000 ssi3_pclk2 ssi3_sfr
ssi3_sfr 0 0 0xb64 0x2000 ssi3_pclk2 ssi3_sfr
usb0_host 0 0 0xb6c 0x20
usb1_host 0 0 0xb6c 0x80
usb0_func 0 0 0xb6c 0x40
usb_pclk 0 0 0xb6c 0x10
eth0_axi 1 1 0xb6c 0x0
eth1_axi 1 1 0xb6c 0x0
i2c0_pclk 0 0 0xb68 0x400
i2c1_pclk 0 0 0xb68 0x800
i2c2_pclk 0 0 0xb68 0x1000
i2c3_pclk 0 0 0xb68 0x2000
scif0_clk_pck 2 1 0xb68 0x0
scif1_clk_pck 0 0 0xb68 0x4
scif2_clk_pck 0 0 0xb68 0x8
scif3_clk_pck 0 0 0xb68 0x10
scif4_clk_pck 0 0 0xb68 0x20
scif5_clk_pck 0 0 0xb90 0x10
adc_adclk 0 0 0xb68 0x4000 adc_adclk adc_pclk
adc_pclk 0 0 0xb68 0x4000 adc_adclk adc_pclk
tsu_pclk 0 0 0xb68 0x8000
vbat_bclk 3 1 0xb90 0x0
Changes in v2:
- updated the title and description for patches 1/8, 2/8 along
with their content
- added patch 3/8
- collected tags
- drop duplicated mstop lists in patch 4/8
- detailed changelog for each patch can be found in the individual
patch
Claudiu Beznea (8):
clk: renesas: rzg2l-cpg: Postone updating priv->clks[]
clk: renesas: rzg2l-cpg: Move pointers after hw member
clk: renesas: rzg2l-cpg: Add macro to loop through module clocks
clk: renesas: rzg2l-cpg: Add support for MSTOP in clock enable/disable
API
clk: renesas: r9a08g045: Drop power domain instantiation
clk: renesas: rzg2l-cpg: Drop MSTOP based power domain support
dt-bindings: clock: rzg2l-cpg: Drop power domain IDs
Revert "dt-bindings: clock: renesas,rzg2l-cpg: Update
#power-domain-cells = <1> for RZ/G3S"
.../bindings/clock/renesas,rzg2l-cpg.yaml | 18 +-
drivers/clk/renesas/r9a07g043-cpg.c | 132 ++---
drivers/clk/renesas/r9a07g044-cpg.c | 168 +++---
drivers/clk/renesas/r9a08g045-cpg.c | 227 ++++----
drivers/clk/renesas/r9a09g011-cpg.c | 116 ++---
drivers/clk/renesas/rzg2l-cpg.c | 487 ++++++++++--------
drivers/clk/renesas/rzg2l-cpg.h | 66 +--
include/dt-bindings/clock/r9a07g043-cpg.h | 53 --
include/dt-bindings/clock/r9a07g044-cpg.h | 58 ---
include/dt-bindings/clock/r9a07g054-cpg.h | 58 ---
include/dt-bindings/clock/r9a08g045-cpg.h | 71 ---
11 files changed, 597 insertions(+), 857 deletions(-)
--
2.43.0
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