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Message-ID: <f2732e5a-7ba9-4ed3-8d33-bd2b996f9a1d@oss.qualcomm.com>
Date: Tue, 27 May 2025 15:34:18 +0200
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: george.moussalem@...look.com, Andrew Lunn <andrew@...n.ch>,
Heiner Kallweit <hkallweit1@...il.com>,
Russell King
<linux@...linux.org.uk>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>,
Florian Fainelli <f.fainelli@...il.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>
Cc: netdev@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-clk@...r.kernel.org
Subject: Re: [PATCH 5/5] arm64: dts: qcom: ipq5018: Add GE PHY to internal
mdio bus
On 5/25/25 7:56 PM, George Moussalem via B4 Relay wrote:
> From: George Moussalem <george.moussalem@...look.com>
>
> The IPQ5018 SoC contains an internal GE PHY, always at phy address 7.
> As such, let's add the GE PHY node to the SoC dtsi.
>
> In addition, the GE PHY outputs both the RX and TX clocks to the GCC
> which gate controls them and routes them back to the PHY itself.
> So let's create two DT fixed clocks and register them in the GCC node.
>
> Signed-off-by: George Moussalem <george.moussalem@...look.com>
> ---
> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 27 +++++++++++++++++++++++++--
> 1 file changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> index 03ebc3e305b267c98a034c41ce47a39269afce75..ff2de44f9b85993fb2d426f85676f7d54c5cf637 100644
> --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> @@ -16,6 +16,18 @@ / {
> #size-cells = <2>;
>
> clocks {
> + gephy_rx_clk: gephy-rx-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <125000000>;
> + #clock-cells = <0>;
> + };
> +
> + gephy_tx_clk: gephy-tx-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <125000000>;
> + #clock-cells = <0>;
> + };
> +
> sleep_clk: sleep-clk {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -192,6 +204,17 @@ mdio0: mdio@...00 {
> clock-names = "gcc_mdio_ahb_clk";
>
> status = "disabled";
> +
> + ge_phy: ethernet-phy@7 {
drop the label unless it needs to be passed somewhere
Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Konrad
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