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Message-ID: <cf68299c-2409-4728-a4d2-c1e9c15ecbdf@amd.com>
Date: Mon, 26 May 2025 20:43:57 -0600
From: Alex Hung <alex.hung@....com>
To: Christophe JAILLET <christophe.jaillet@...adoo.fr>,
Harry Wentland <harry.wentland@....com>, Leo Li <sunpeng.li@....com>,
Rodrigo Siqueira <siqueira@...lia.com>,
Alex Deucher <alexander.deucher@....com>,
Christian König <christian.koenig@....com>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>
Cc: linux-kernel@...r.kernel.org, kernel-janitors@...r.kernel.org,
amd-gfx@...ts.freedesktop.org, dri-devel@...ts.freedesktop.org
Subject: Re: [PATCH] drm/amd/display: Constify struct timing_generator_funcs
Reviewed-by: Alex Hung <alex.hung@....com>
On 5/24/25 10:51, Christophe JAILLET wrote:
> 'struct timing_generator_funcs' are not modified in these drivers.
>
> Constifying these structures moves some data to a read-only section, so
> increases overall security, especially when the structure holds some
> function pointers.
>
> Signed-off-by: Christophe JAILLET <christophe.jaillet@...adoo.fr>
> ---
> This is NOT compile tested, because apparently some .h files are missing on
> my system ("reg_helper.h")
>
> However, I've checked how these struct timing_generator_funcs are used.
> They end in "struct optc->base.funcs" which is a
> "const struct timing_generator_funcs", so evething should be fine.
> ---
> drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c | 2 +-
> drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c | 2 +-
> drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c | 2 +-
> drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c | 2 +-
> drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c | 2 +-
> drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c | 2 +-
> drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c | 2 +-
> drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c | 2 +-
> drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c | 2 +-
> 9 files changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
> index 81857ce6d68d..e7a90a437fff 100644
> --- a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
> +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
> @@ -502,7 +502,7 @@ void optc2_get_last_used_drr_vtotal(struct timing_generator *optc, uint32_t *ref
> REG_GET(OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, refresh_rate);
> }
>
> -static struct timing_generator_funcs dcn20_tg_funcs = {
> +static const struct timing_generator_funcs dcn20_tg_funcs = {
> .validate_timing = optc1_validate_timing,
> .program_timing = optc1_program_timing,
> .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
> diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
> index f2415eebdc09..772a8bfb949c 100644
> --- a/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
> +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c
> @@ -129,7 +129,7 @@ static void optc201_get_optc_source(struct timing_generator *optc,
> *num_of_src_opp = 1;
> }
>
> -static struct timing_generator_funcs dcn201_tg_funcs = {
> +static const struct timing_generator_funcs dcn201_tg_funcs = {
> .validate_timing = optc201_validate_timing,
> .program_timing = optc1_program_timing,
> .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
> diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
> index 78b58a449fa4..ee4665aa49e9 100644
> --- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
> +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c
> @@ -357,7 +357,7 @@ void optc3_tg_init(struct timing_generator *optc)
> optc1_clear_optc_underflow(optc);
> }
>
> -static struct timing_generator_funcs dcn30_tg_funcs = {
> +static const struct timing_generator_funcs dcn30_tg_funcs = {
> .validate_timing = optc1_validate_timing,
> .program_timing = optc1_program_timing,
> .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
> diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c
> index 65e9089b7f31..38f85bc2681a 100644
> --- a/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c
> +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c
> @@ -109,7 +109,7 @@ void optc301_setup_manual_trigger(struct timing_generator *optc)
> OTG_TRIGA_CLEAR, 1);
> }
>
> -static struct timing_generator_funcs dcn30_tg_funcs = {
> +static const struct timing_generator_funcs dcn30_tg_funcs = {
> .validate_timing = optc1_validate_timing,
> .program_timing = optc1_program_timing,
> .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
> diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
> index ef536f37b4ed..4f1830ba619f 100644
> --- a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
> +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c
> @@ -315,7 +315,7 @@ void optc31_read_otg_state(struct timing_generator *optc,
> s->otg_double_buffer_control = REG_READ(OTG_DOUBLE_BUFFER_CONTROL);
> }
>
> -static struct timing_generator_funcs dcn31_tg_funcs = {
> +static const struct timing_generator_funcs dcn31_tg_funcs = {
> .validate_timing = optc1_validate_timing,
> .program_timing = optc1_program_timing,
> .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
> diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c
> index 0e603bad0d12..4a2caca37255 100644
> --- a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c
> +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c
> @@ -192,7 +192,7 @@ static void optc314_set_h_timing_div_manual_mode(struct timing_generator *optc,
> }
>
>
> -static struct timing_generator_funcs dcn314_tg_funcs = {
> +static const struct timing_generator_funcs dcn314_tg_funcs = {
> .validate_timing = optc1_validate_timing,
> .program_timing = optc1_program_timing,
> .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
> diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
> index 2cdd19ba634b..b2b226bcd871 100644
> --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
> +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
> @@ -297,7 +297,7 @@ static void optc32_set_drr(
> optc32_setup_manual_trigger(optc);
> }
>
> -static struct timing_generator_funcs dcn32_tg_funcs = {
> +static const struct timing_generator_funcs dcn32_tg_funcs = {
> .validate_timing = optc1_validate_timing,
> .program_timing = optc1_program_timing,
> .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
> diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
> index 4cfc6c0fa147..72bff94cb57d 100644
> --- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
> +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
> @@ -428,7 +428,7 @@ static void optc35_set_long_vtotal(
> }
> }
>
> -static struct timing_generator_funcs dcn35_tg_funcs = {
> +static const struct timing_generator_funcs dcn35_tg_funcs = {
> .validate_timing = optc1_validate_timing,
> .program_timing = optc1_program_timing,
> .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
> diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
> index 382ac18e7854..ff79c38287df 100644
> --- a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
> +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
> @@ -459,7 +459,7 @@ bool optc401_wait_update_lock_status(struct timing_generator *tg, bool locked)
> return true;
> }
>
> -static struct timing_generator_funcs dcn401_tg_funcs = {
> +static const struct timing_generator_funcs dcn401_tg_funcs = {
> .validate_timing = optc1_validate_timing,
> .program_timing = optc1_program_timing,
> .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
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