linux-kernel - Re: [PATCH 3/3] arm64: dts: imx95: add SMMU support for NETC

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Message-ID: <aDcnMnAJO+YVQ6rJ@lizhi-Precision-Tower-5810>
Date: Wed, 28 May 2025 11:09:38 -0400
From: Frank Li <Frank.li@....com>
To: Wei Fang <wei.fang@....com>
Cc: robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
	shawnguo@...nel.org, s.hauer@...gutronix.de, kernel@...gutronix.de,
	festevam@...il.com, devicetree@...r.kernel.org, imx@...ts.linux.dev,
	linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 3/3] arm64: dts: imx95: add SMMU support for NETC

On Wed, May 28, 2025 at 04:34:33PM +0800, Wei Fang wrote:
> The i.MX95 NETC supports SMMU, so add SMMU support.
>
> Signed-off-by: Wei Fang <wei.fang@....com>
> ---
>  arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts | 8 ++++++++
>  arch/arm64/boot/dts/freescale/imx95.dtsi          | 8 ++++++++
>  2 files changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> index 9f4d0899a94d..e9a5fb36f5d0 100644
> --- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
> @@ -494,6 +494,14 @@ &netc_bus0 {
>  		  <0x60 &its 0x66 0x1>, //ENETC1 VF1
>  		  <0x80 &its 0x64 0x1>, //ENETC2 PF
>  		  <0xc0 &its 0x67 0x1>;
> +	iommu-map = <0x0 &smmu 0x20 0x1>,
> +		    <0x10 &smmu 0x21 0x1>,
> +		    <0x20 &smmu 0x22 0x1>,
> +		    <0x40 &smmu 0x23 0x1>,
> +		    <0x50 &smmu 0x25 0x1>,
> +		    <0x60 &smmu 0x26 0x1>,
> +		    <0x80 &smmu 0x24 0x1>,
> +		    <0xc0 &smmu 0x27 0x1>;

Do you need iommu-map-mask to mask bus id in case difference probe order
with pcie node?

Frank Li


>  };
>
>  &netc_emdio {
> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> index 632631a29112..32a91d7b51e5 100644
> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> @@ -1861,6 +1861,14 @@ netc_bus0: pcie@...00000 {
>  					  <0x90 &its 0x65 0x1>, //ENETC2 VF0
>  					  <0xa0 &its 0x66 0x1>, //ENETC2 VF1
>  					  <0xc0 &its 0x67 0x1>; //NETC Timer
> +				iommu-map = <0x0 &smmu 0x20 0x1>,
> +					    <0x10 &smmu 0x21 0x1>,
> +					    <0x20 &smmu 0x22 0x1>,
> +					    <0x40 &smmu 0x23 0x1>,
> +					    <0x80 &smmu 0x24 0x1>,
> +					    <0x90 &smmu 0x25 0x1>,
> +					    <0xa0 &smmu 0x26 0x1>,
> +					    <0xc0 &smmu 0x27 0x1>;
>  					 /* ENETC0~2 and Timer BAR0 - non-prefetchable memory */
>  				ranges = <0x82000000 0x0 0x4cc00000  0x0 0x4cc00000  0x0 0xe0000
>  					 /* Timer BAR2 - prefetchable memory */
> --
> 2.34.1
>