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Message-ID: <CA+V-a8uKzGxbU5A9nRTRL2azykGdhMmawni2ME4T2jqJxBBtew@mail.gmail.com>
Date: Wed, 28 May 2025 18:43:59 +0100
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: Fabrizio Castro <fabrizio.castro.jz@...esas.com>, Andrzej Hajda <andrzej.hajda@...el.com>,
Neil Armstrong <neil.armstrong@...aro.org>, Robert Foss <rfoss@...nel.org>,
Laurent Pinchart <Laurent.pinchart@...asonboard.com>, Jonas Karlman <jonas@...boo.se>,
Jernej Skrabec <jernej.skrabec@...il.com>, David Airlie <airlied@...il.com>,
Simona Vetter <simona@...ll.ch>, Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
Biju Das <biju.das.jz@...renesas.com>, Magnus Damm <magnus.damm@...il.com>,
dri-devel@...ts.freedesktop.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-renesas-soc@...r.kernel.org,
linux-clk@...r.kernel.org,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v5 4/4] drm: renesas: rz-du: mipi_dsi: Add support for
RZ/V2H(P) SoC
Hi Geert,
On Wed, May 28, 2025 at 1:32 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Wed, 28 May 2025 at 11:48, Lad, Prabhakar <prabhakar.csengg@...il.com> wrote:
> > On Fri, May 23, 2025 at 4:19 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
> > > On Mon, 12 May 2025 at 20:43, Prabhakar <prabhakar.csengg@...il.com> wrote:
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > > >
> > > > Add DSI support for Renesas RZ/V2H(P) SoC.
> > > >
> > > > Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@...esas.com>
> > > > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@...esas.com>
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > >
> > > Thanks for your patch!
> > >
> > > > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> > > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
>
> > > > @@ -47,6 +52,11 @@ struct rzg2l_mipi_dsi_hw_info {
> > > > u8 features;
> > > > };
> > > >
> > > > +struct rzv2h_dsi_mode_calc {
> > > > + unsigned long mode_freq;
> > > > + u64 mode_freq_hz;
> > >
> > > Interesting... I guess mode_freq is not in Hz?
> > >
> > Actually it is int Hz, I will make it unsigned long.
>
> I really meant the first member.
> As rzv2h_dphy_mode_clk_check() does "mode_freq_hz = mode_freq * MILLI",
> mode_freq may be in kHz?
>
Sorry, I got confused. mode_freq is in kHz probably I'll rename this
to make it clear.
> > > > +};
>
> > > > @@ -308,6 +479,158 @@ static int rzg2l_dphy_conf_clks(struct rzg2l_mipi_dsi *dsi, unsigned long mode_f
> > > > return 0;
> > > > }
> > > >
> > > > +static unsigned int rzv2h_dphy_mode_clk_check(struct rzg2l_mipi_dsi *dsi,
> > > > + unsigned long mode_freq)
> > > > +{
> > > > + struct rzv2h_plldsi_parameters *dsi_parameters = &dsi->dsi_parameters;
> > > > + u64 hsfreq_millihz, mode_freq_hz, mode_freq_millihz;
> > > > + struct rzv2h_plldsi_parameters cpg_dsi_parameters;
> > > > + unsigned int bpp, i;
> > > > +
> > > > + bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
> > > > +
> > > > + for (i = 0; i < 10; i += 1) {
> > > > + unsigned long hsfreq;
> > > > + bool parameters_found;
> > > > +
> > > > + mode_freq_hz = mode_freq * MILLI + i;
> > >
> > > KILO?
> > >
> > OK, as mode_freq_hz is in Hz I'll make it unsigned long.
>
> I am not sure if "unsigned long" is OK. Is mode_freq in kHz?
> What is its largest value?
>
Sorry I got confused, I will reinstate mode_freq_hz to be u64. The
largest value can depend on the max resolution by the display.
Cheers,
Prabhakar
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