linux-kernel - Re: [PATCH] arm64: dts: qcom: qcs615: disable the CTI device of the camera block

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Message-ID: <79f5e42f-f857-4247-abf9-d0f3f5c1a498@quicinc.com>
Date: Wed, 28 May 2025 11:02:14 +0800
From: Jie Gan <quic_jiegan@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
        Jie Gan
	<jie.gan@....qualcomm.com>,
        Bjorn Andersson <andersson@...nel.org>,
        "Konrad
 Dybcio" <konradybcio@...nel.org>,
        Rob Herring <robh@...nel.org>,
        "Krzysztof
 Kozlowski" <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>
CC: Tingwei Zhang <quic_tingweiz@...cinc.com>,
        Jinlong Mao
	<quic_jinlmao@...cinc.com>,
        <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] arm64: dts: qcom: qcs615: disable the CTI device of the
 camera block



On 5/27/2025 6:41 PM, Konrad Dybcio wrote:
> On 5/27/25 12:32 PM, Jie Gan wrote:
>>
>>
>> On 5/27/2025 6:23 PM, Konrad Dybcio wrote:
>>> On 5/27/25 3:52 AM, Jie Gan wrote:
>>>> Disable the CTI device of the camera block to prevent potential NoC errors
>>>> during AMBA bus device matching.
>>>>
>>>> The clocks for the Qualcomm Debug Subsystem (QDSS) are managed by aoss_qmp
>>>> through a mailbox. However, the camera block resides outside the AP domain,
>>>> meaning its QDSS clock cannot be controlled via aoss_qmp.
>>>
>>> Which clock drives it then?
>>
>> It's qcom,aoss-qmp.
>>
>> clk_prepare->qmp_qdss_clk_prepare
>> https://elixir.bootlin.com/linux/v6.15-rc7/source/drivers/soc/qcom/qcom_aoss.c#L280
> 
> I'm confused about this part:
> 
>> However, the camera block resides outside the AP domain,
>> meaning its QDSS clock cannot be controlled via aoss_qmp.
> 
> Do we need to poke the QMP of another DRV?

The AOSS has a clock control register for all QDSS clocks. when we vote 
the qdss clock, the aoss_qmp driver will send a message to AOSS to 
enable the clock control register, then the clock control register will 
enable all QDSS clocks.

The QDSS clock is not a single clock source, it is a term that 
representing all the clock sources utilized by the QDSS.

Thanks,
Jie

> 
> Konrad