linux-kernel - Re: [PATCH 09/10] PCI: exynos: Add support for Tesla FSD SoC

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Message-ID: <441dd5c3-fd51-4471-86ad-337c646b1571@kernel.org>
Date: Wed, 28 May 2025 09:25:35 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Shradha Todi <shradha.t@...sung.com>
Cc: linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, linux-samsung-soc@...r.kernel.or,
 linux-kernel@...r.kernel.org, linux-phy@...ts.infradead.org,
 manivannan.sadhasivam@...aro.org, lpieralisi@...nel.org, kw@...ux.com,
 robh@...nel.org, bhelgaas@...gle.com, jingoohan1@...il.com,
 krzk+dt@...nel.org, conor+dt@...nel.org, alim.akhtar@...sung.com,
 vkoul@...nel.org, kishon@...nel.org, arnd@...db.de,
 m.szyprowski@...sung.com, jh80.chung@...sung.com
Subject: Re: [PATCH 09/10] PCI: exynos: Add support for Tesla FSD SoC

On 27/05/2025 12:45, Shradha Todi wrote:
> 
> 
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzk@...nel.org>
>> Sent: 21 May 2025 15:18
>> To: Shradha Todi <shradha.t@...sung.com>
>> Cc: linux-pci@...r.kernel.org; devicetree@...r.kernel.org; linux-arm-kernel@...ts.infradead.org; linux-samsung-soc@...r.kernel.or;
>> linux-kernel@...r.kernel.org; linux-phy@...ts.infradead.org; manivannan.sadhasivam@...aro.org; lpieralisi@...nel.org;
>> kw@...ux.com; robh@...nel.org; bhelgaas@...gle.com; jingoohan1@...il.com; krzk+dt@...nel.org; conor+dt@...nel.org;
>> alim.akhtar@...sung.com; vkoul@...nel.org; kishon@...nel.org; arnd@...db.de; m.szyprowski@...sung.com;
>> jh80.chung@...sung.com
>> Subject: Re: [PATCH 09/10] PCI: exynos: Add support for Tesla FSD SoC
>>
>> On Mon, May 19, 2025 at 01:01:51AM GMT, Shradha Todi wrote:
>>>  static int exynos_pcie_probe(struct platform_device *pdev)  {
>>>  	struct device *dev = &pdev->dev;
>>> @@ -355,6 +578,26 @@ static int exynos_pcie_probe(struct platform_device *pdev)
>>>  	if (IS_ERR(ep->phy))
>>>  		return PTR_ERR(ep->phy);
>>>
>>> +	if (ep->pdata->soc_variant == FSD) {
>>> +		ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
>>> +		if (ret)
>>> +			return ret;
>>> +
>>> +		ep->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
>>> +				"samsung,syscon-pcie");
>>> +		if (IS_ERR(ep->sysreg)) {
>>> +			dev_err(dev, "sysreg regmap lookup failed.\n");
>>> +			return PTR_ERR(ep->sysreg);
>>> +		}
>>> +
>>> +		ret = of_property_read_u32_index(dev->of_node, "samsung,syscon-pcie", 1,
>>> +						 &ep->sysreg_offset);
>>> +		if (ret) {
>>> +			dev_err(dev, "couldn't get the register offset for syscon!\n");
>>
>> So all MMIO will go via syscon? I am pretty close to NAKing all this, but let's be sure that I got it right - please post your complete DTS
>> for upstream. That's a requirement from me for any samsung drivers - I don't want to support fake, broken downstream solutions
>> (based on multiple past submissions).
>>
> 
> By all MMIO do you mean DBI read/write? The FSD hardware architecture is such that the DBI/ATU/DMA address is at the same offset.
> The syscon register holds the upper bits of the actual address differentiating between these 3 spaces. This kind of implementation was done
> to reduce address space for PCI DWC controller. So yes, each DBI/ATU register read/write will have syscon write before it to switch address space.

Wrap your replies correctly to fit mailing list.

No, I meant your binding does not define any MMIO at all. I see you use
for example elbi_base which is mapped from "elbi" reg entry, but you do
not have it in your binding.

Maybe just binding is heavily incomplete and that confused me.

Best regards,
Krzysztof