linux-kernel - Re:Re: [PATCH v2] arm64: dts: rockchip: Adjust the HDMI DDC IO driver strength for rk3588

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Message-ID: <9ffd480.852d.19716157087.Coremail.andyshrk@163.com>
Date: Wed, 28 May 2025 16:49:53 +0800 (CST)
From: "Andy Yan" <andyshrk@....com>
To: "Nicolas Frattaroli" <nicolas.frattaroli@...labora.com>
Cc: heiko@...ech.de, linux-rockchip@...ts.infradead.org, simic@...jaro.org,
	krzk+dt@...nel.org, robh@...nel.org, devicetree@...r.kernel.org,
	conor+dt@...nel.org, linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org, algea.cao@...k-chips.com,
	"Andy Yan" <andy.yan@...k-chips.com>
Subject: Re:Re: [PATCH v2] arm64: dts: rockchip: Adjust the HDMI DDC IO
 driver strength for rk3588


Hello Nicolas,

At 2025-05-27 19:53:56, "Nicolas Frattaroli" <nicolas.frattaroli@...labora.com> wrote:
>On Thursday, 22 May 2025 04:05:24 Central European Summer Time Andy Yan wrote:
>> From: Andy Yan <andy.yan@...k-chips.com>
>> 
>> For the RK3588 HDMI controller, the falling edge of DDC SDA and SCL
>> almost coincide and cannot be adjusted by HDMI registrer, resulting
>> in poor compatibility of DDC communication.
>> 
>> An improvement of the compatibility of DDC can be done by increasing
>> the driver strength of SCL and decreasing the driver strength of SDA
>> to increase the slope of the falling edge.
>> 
>> It should be noted that the maximum driving strength of hdmim0_tx1_scl
>> is only 3, which is different from that of the other IOs.
>> 
>> Signed-off-by: Andy Yan <andy.yan@...k-chips.com>
>> 
>> ---
>> 
>> Changes in v2:
>> - Correct the max drive level of hdmim0_tx1_scl.
>> 
>>  .../dts/rockchip/rk3588-base-pinctrl.dtsi     | 20 +++++------
>>  .../dts/rockchip/rk3588-extra-pinctrl.dtsi    |  5 +--
>>  .../boot/dts/rockchip/rockchip-pinconf.dtsi   | 35 +++++++++++++++++++
>>  3 files changed, 48 insertions(+), 12 deletions(-)
>> 
>
>Tested-by: Nicolas Frattaroli <nicolas.frattaroli@...labora.com>
>
>Quickly tested this on both HDMI ports of a ROCK 5T with an HDMI capture
>card on the other end. While I didn't originally have any issues to begin
>with, this patch does not introduce any new ones, so seems good to me.


Thanks for yout test.

I sent this patch because someone from the community reported to me that his board
couldn't successfully establish ddc communication when running the mainline kernel.
After conducting extensive comparisons, it was discovered that there were differences
in the IO drive strength configuration between mainline code and the downstream code. 
Then, I recalled that during the chip bringup process and when conducting the SI test, 
we had encountered this problem before, and we did the fix by adjusting DDC IO drive strength.
>