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Message-ID: <4c93cea1-a27a-42dc-8248-06b23da3a558@kernel.org>
Date: Wed, 28 May 2025 11:09:08 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Albert Yang <yangzh0906@...ndersoft.com>, Arnd Bergmann <arnd@...db.de>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Ge Gordon <gordon.ge@....ai>
Cc: BST Linux Kernel Upstream Group <bst-upstream@...ai.top>,
linux-arm-kernel@...ts.infradead.org, soc@...ts.linux.dev,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1 6/9] arm64: dts: bst: add support for Black Sesame
Technologies C1200 CDCU1.0 board
On 28/05/2025 10:54, Albert Yang wrote:
> Add device tree support for the Black Sesame Technologies (BST) C1200
> CDCU1.0 ADAS 4C2G platform. This platform is based on the BST C1200 SoC
> family.
>
> The changes include:
> - Adding a new BST device tree directory
> - Adding Makefile entries to build the BST platform device trees
> - Adding the device tree for the BST C1200 CDCU1.0 ADAS 4C2G board
>
> This board features a quad-core Cortex-A78 CPU, and various peripherals
> including UART, MMC, watchdog timer, and interrupt controller.
>
> Signed-off-by: Ge Gordon <gordon.ge@....ai>
> Signed-off-by: Albert Yang <yangzh0906@...ndersoft.com>
> ---
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/bst/Makefile | 10 ++
> .../dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts | 44 ++++++
> arch/arm64/boot/dts/bst/bstc1200.dtsi | 130 ++++++++++++++++++
> 4 files changed, 185 insertions(+)
> create mode 100644 arch/arm64/boot/dts/bst/Makefile
> create mode 100644 arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts
> create mode 100644 arch/arm64/boot/dts/bst/bstc1200.dtsi
>
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 79b73a21ddc2..135965288100 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -35,3 +35,4 @@ subdir-y += tesla
> subdir-y += ti
> subdir-y += toshiba
> subdir-y += xilinx
> +subdir-y += bst
Don't add to random places or at the end, but place entries in
alphabetical order.
> diff --git a/arch/arm64/boot/dts/bst/Makefile b/arch/arm64/boot/dts/bst/Makefile
> new file mode 100644
> index 000000000000..64fd43c98275
> --- /dev/null
> +++ b/arch/arm64/boot/dts/bst/Makefile
> @@ -0,0 +1,10 @@
> +ifeq ($(CONFIG_SECOND_KERNEL), )
There is no such thing.
> +
> +# Enables support for device-tree overlays
> +DTC_FLAGS := -@
> +
> +dtb-$(CONFIG_ARCH_BSTC1200) += bstc1200-cdcu1.0-adas_4c2g.dtb
> +
> +endif
> +
> +clean-files := *.dtb
Why?
> diff --git a/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts
> new file mode 100644
> index 000000000000..92915e7630ff
> --- /dev/null
> +++ b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts
> @@ -0,0 +1,44 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/dts-v1/;
> +
> +#include "bstc1200.dtsi"
> +
> +/ {
> + model = "BST C1200-96 CDCU1.0 4C2G";
> +
> + chosen {
> + bootargs = "earlycon=uart8250,mmio32,0x20008000 console=ttyS0,115200n8 rw";
Earlycon is debugging, why do you need it for general use?
console: redundant
rw: not suitable for DT
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory@...000000 {
> + device_type = "memory";
> + reg = <0x8 0x10000000 0x0 0x30000000
> + 0x8 0xc0000000 0x1 0x0
> + 0xc 0x0 0x0 0x40000000
> + 0x8 0x254000 0x0 0x1000
> + 0x8 0x151000 0x0 0x1000>;
Multiple entries go into multiple entries <>.
> + };
> +
> + reserved-memory {
> + #address-cells = <0x2>;
> + #size-cells = <0x2>;
> + ranges;
> +
> + mmc0_reserved: mmc0_region@...0000 {
Follow DTS coding style. Also drop redundant "region"
> + compatible = "shared-dma-pool";
> + reg = <0x0 0x5160000 0x0 0x10000>;
> + no-map;
> + };
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> +&mmc0 {
> + status = "okay";
> + memory-region = <&mmc0_reserved>;
> +};
> +
> diff --git a/arch/arm64/boot/dts/bst/bstc1200.dtsi b/arch/arm64/boot/dts/bst/bstc1200.dtsi
> new file mode 100644
> index 000000000000..6ed2d8cbd720
> --- /dev/null
> +++ b/arch/arm64/boot/dts/bst/bstc1200.dtsi
> @@ -0,0 +1,130 @@
> +// SPDX-License-Identifier: GPL-2.0
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +/ {
> + compatible = "bst,c1200";
> + #address-cells = <0x2>;
> + #size-cells = <0x2>;
These are not hex.
> +
> + cpus {
> + #address-cells = <0x1>;
> + #size-cells = <0x0>;
Same comments
> +
> + cpu@0 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + enable-method = "psci";
> + next-level-cache = <&l2_cache>;
> + reg = <0x0>;
> + freq-domain = <0x3 0x1>;
> + };
> +
> + cpu@1 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + enable-method = "psci";
> + next-level-cache = <&l2_cache>;
> + reg = <0x100>;
> + freq-domain = <0x3 0x1>;
> + };
> +
> + cpu@2 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + enable-method = "psci";
> + next-level-cache = <&l2_cache>;
> + reg = <0x200>;
> + freq-domain = <0x3 0x1>;
> + };
> +
> + cpu@3 {
> + compatible = "arm,cortex-a78";
> + device_type = "cpu";
> + enable-method = "psci";
> + next-level-cache = <&l2_cache>;
> + reg = <0x300>;
> + freq-domain = <0x3 0x1>;
> + };
> +
> + l2_cache: l2-cache-1 {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + };
> + };
> +
> + misc_clk: misc_clk {
Follow DTS coding style. Please use name for all fixed clocks which
matches current format recommendation: 'clock-<freq>' (see also the
pattern in the binding for any other options).
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml?h=v6.11-rc1
> + compatible = "fixed-clock";
> + #clock-cells = <0x0>;
> + clock-frequency = <0x3d0900>;
This is not a hex.
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupt-parent = <&gic>;
> + always-on;
> + interrupts = <GIC_PPI 0xd (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)
> + GIC_PPI 0xe (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)
> + GIC_PPI 0xb (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)
> + GIC_PPI 0xa (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + soc: soc@0 {
> + compatible = "simple-bus";
> + #address-cells = <0x2>;
> + #size-cells = <0x2>;
> + ranges = <0x0 0x0 0x0 0x0 0xffffffff 0xffffffff>;
Follow DTS coding style
> +
> + mmc0: dwmmc0@...00000 {
It does not look like you tested the DTS against bindings. Please run
`make dtbs_check W=1` (see
Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).
Maybe you need to update your dtschema and yamllint. Don't rely on
distro packages for dtschema and be sure you are using the latest
released dtschema.
Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> + #address-cells = <0x2>;
> + #size-cells = <0x0>;
> + compatible = "bst,dwcmshc-sdhci";
> + reg = <0x0 0x22200000 0x0 0x1000>;
> + reg-names = "base";
Order properties according to DTS coding style.
Best regards,
Krzysztof
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