linux-kernel - Re: [PATCH v5 3/7] coresight-tgu: Add signal priority support

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Message-ID: <20250529122950.00001fe6@huawei.com>
Date: Thu, 29 May 2025 12:29:50 +0100
From: Jonathan Cameron <Jonathan.Cameron@...wei.com>
To: Songwei Chai <quic_songchai@...cinc.com>
CC: Suzuki K Poulose <suzuki.poulose@....com>, Mike Leach
	<mike.leach@...aro.org>, James Clark <james.clark@....com>, "Alexander
 Shishkin" <alexander.shishkin@...ux.intel.com>, Andy Gross
	<agross@...nel.org>, Bjorn Andersson <andersson@...nel.org>, Rob Herring
	<robh+dt@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, "Conor
 Dooley" <conor+dt@...nel.org>, <linux-kernel@...r.kernel.org>,
	<coresight@...ts.linaro.org>, <linux-arm-kernel@...ts.infradead.org>,
	<linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>
Subject: Re: [PATCH v5 3/7] coresight-tgu: Add signal priority support

On Thu, 29 May 2025 16:19:44 +0800
Songwei Chai <quic_songchai@...cinc.com> wrote:

> Like circuit of a Logic analyzer, in TGU, the requirement could be
> configured in each step and the trigger will be created once the
> requirements are met. Add priority functionality here to sort the
> signals into different priorities. The signal which is wanted could
> be configured in each step's priority node, the larger number means
> the higher priority and the signal with higher priority will be sensed
> more preferentially.
> 
> Signed-off-by: Songwei Chai <quic_songchai@...cinc.com>


> diff --git a/drivers/hwtracing/coresight/coresight-tgu.h b/drivers/hwtracing/coresight/coresight-tgu.h
> index 6c849a2f78fa..f07ead505365 100644
> --- a/drivers/hwtracing/coresight/coresight-tgu.h
> +++ b/drivers/hwtracing/coresight/coresight-tgu.h
> @@ -13,6 +13,112 @@

> +enum operation_index {
> +	TGU_PRIORITY0,
> +	TGU_PRIORITY1,
> +	TGU_PRIORITY2,
> +	TGU_PRIORITY3
No blank line.  Also convention on anything other than a terminating entry
is to leave the trailing , 
> +
> +};

> +
>  /**
>   * struct tgu_drvdata - Data structure for a TGU (Trigger Generator Unit)
>   * @base: Memory-mapped base address of the TGU device
> @@ -20,6 +126,9 @@
>   * @csdev: Pointer to the associated coresight device
>   * @spinlock: Spinlock for handling concurrent access
>   * @enable: Flag indicating whether the TGU device is enabled
> + * @value_table: Store given value based on relevant parameters.
> + * @max_reg: Maximum number of registers
> + * @max_step: Maximum step size
>   *
>   * This structure defines the data associated with a TGU device,
>   * including its base address, device pointers, clock, spinlock for
> @@ -32,6 +141,9 @@ struct tgu_drvdata {
>  	struct coresight_device *csdev;
>  	spinlock_t spinlock;
>  	bool enable;
> +	struct value_table *value_table;
> +	int max_reg;
> +	int max_step;

Ah. Here some of the bits missing in previous patch that make
the description make more sense.  Fair enough.

>  };
>  
>  #endif
> 
>