linux-kernel - Re: [PATCH 2/2] perf/x86/intel: Fix wrong index calculation in intel_pmu_config

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Message-ID: <8f94b5b7-0552-4860-8ff1-bec83e3abb3e@linux.intel.com>
Date: Thu, 29 May 2025 09:55:09 -0400
From: "Liang, Kan" <kan.liang@...ux.intel.com>
To: Dapeng Mi <dapeng1.mi@...ux.intel.com>,
 Peter Zijlstra <peterz@...radead.org>, Ingo Molnar <mingo@...hat.com>,
 Arnaldo Carvalho de Melo <acme@...nel.org>,
 Namhyung Kim <namhyung@...nel.org>, Ian Rogers <irogers@...gle.com>,
 Adrian Hunter <adrian.hunter@...el.com>,
 Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
 Andi Kleen <ak@...ux.intel.com>, Eranian Stephane <eranian@...gle.com>
Cc: linux-kernel@...r.kernel.org, linux-perf-users@...r.kernel.org,
 Dapeng Mi <dapeng1.mi@...el.com>
Subject: Re: [PATCH 2/2] perf/x86/intel: Fix wrong index calculation in
 intel_pmu_config_acr()



On 2025-05-29 4:02 a.m., Dapeng Mi wrote:
> To calculate fixed counter MSR address, the HW counter index "idx" is
> subtracted by INTEL_PMC_IDX_FIXED. It leads to the ACR mask value of
> fixed counters is incorrectly saved to the positions of GP counters
> in acr_cfg_b[], e.g. For fixed counter 0, its ACR counter mask should be
> saved to acr_cfg_b[32], but it's saved to acr_cfg_b[0] incorrectly.
> 
> Fix this issue.
> 
> Fixes: ec980e4facef ("perf/x86/intel: Support auto counter reload")
> Signed-off-by: Dapeng Mi <dapeng1.mi@...ux.intel.com>

Reviewed-by: Kan Liang <kan.liang@...ux.intel.com>

Thanks,
Kan

> ---
>  arch/x86/events/intel/core.c | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index 8d046b1a237e..b0fee684ec8c 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -2899,6 +2899,7 @@ static void intel_pmu_config_acr(int idx, u64 mask, u32 reload)
>  {
>  	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
>  	int msr_b, msr_c;
> +	int msr_offset;
>  
>  	if (!mask && !cpuc->acr_cfg_b[idx])
>  		return;
> @@ -2906,19 +2907,20 @@ static void intel_pmu_config_acr(int idx, u64 mask, u32 reload)
>  	if (idx < INTEL_PMC_IDX_FIXED) {
>  		msr_b = MSR_IA32_PMC_V6_GP0_CFG_B;
>  		msr_c = MSR_IA32_PMC_V6_GP0_CFG_C;
> +		msr_offset = x86_pmu.addr_offset(idx, false);
>  	} else {
>  		msr_b = MSR_IA32_PMC_V6_FX0_CFG_B;
>  		msr_c = MSR_IA32_PMC_V6_FX0_CFG_C;
> -		idx -= INTEL_PMC_IDX_FIXED;
> +		msr_offset = x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false);
>  	}
>  
>  	if (cpuc->acr_cfg_b[idx] != mask) {
> -		wrmsrl(msr_b + x86_pmu.addr_offset(idx, false), mask);
> +		wrmsrl(msr_b + msr_offset, mask);
>  		cpuc->acr_cfg_b[idx] = mask;
>  	}
>  	/* Only need to update the reload value when there is a valid config value. */
>  	if (mask && cpuc->acr_cfg_c[idx] != reload) {
> -		wrmsrl(msr_c + x86_pmu.addr_offset(idx, false), reload);
> +		wrmsrl(msr_c + msr_offset, reload);
>  		cpuc->acr_cfg_c[idx] = reload;
>  	}
>  }