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Message-ID: <202505292205.MoljmkjQ-lkp@intel.com>
Date: Thu, 29 May 2025 23:03:51 +0800
From: kernel test robot <lkp@...el.com>
To: Raag Jadav <raag.jadav@...el.com>
Cc: oe-kbuild-all@...ts.linux.dev, linux-kernel@...r.kernel.org,
Rodrigo Vivi <rodrigo.vivi@...el.com>,
Riana Tauro <riana.tauro@...el.com>
Subject: drivers/gpu/drm/xe/xe_device_sysfs.c:118:66-71: WARNING: conversion
to bool not needed here
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 90b83efa6701656e02c86e7df2cb1765ea602d07
commit: 0e414bf7ad012e55c8a0aa4e91f68cb1cf5801ff drm/xe: Expose PCIe link downgrade attributes
date: 3 weeks ago
config: loongarch-randconfig-r053-20250529 (https://download.01.org/0day-ci/archive/20250529/202505292205.MoljmkjQ-lkp@intel.com/config)
compiler: loongarch64-linux-gcc (GCC) 15.1.0
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@...el.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202505292205.MoljmkjQ-lkp@intel.com/
cocci warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/xe/xe_device_sysfs.c:118:66-71: WARNING: conversion to bool not needed here
vim +118 drivers/gpu/drm/xe/xe_device_sysfs.c
67
68 /**
69 * DOC: PCIe Gen5 Limitations
70 *
71 * Default link speed of discrete GPUs is determined by configuration parameters
72 * stored in their flash memory, which are subject to override through user
73 * initiated firmware updates. It has been observed that devices configured with
74 * PCIe Gen5 as their default link speed can come across link quality issues due
75 * to host or motherboard limitations and may have to auto-downgrade their link
76 * to PCIe Gen4 speed when faced with unstable link at Gen5, which makes
77 * firmware updates rather risky on such setups. It is required to ensure that
78 * the device is capable of auto-downgrading its link to PCIe Gen4 speed before
79 * pushing the firmware image with PCIe Gen5 as default configuration. This can
80 * be done by reading ``auto_link_downgrade_capable`` sysfs entry, which will
81 * denote if the device is capable of auto-downgrading its link to PCIe Gen4
82 * speed with boolean output value of ``0`` or ``1``, meaning `incapable` or
83 * `capable` respectively.
84 *
85 * .. code-block:: shell
86 *
87 * $ cat /sys/bus/pci/devices/<bdf>/auto_link_downgrade_capable
88 *
89 * Pushing the firmware image with PCIe Gen5 as default configuration on a auto
90 * link downgrade incapable device and facing link instability due to host or
91 * motherboard limitations can result in driver failing to bind to the device,
92 * making further firmware updates impossible with RMA being the only last
93 * resort.
94 *
95 * Link downgrade status of auto link downgrade capable devices is available
96 * through ``auto_link_downgrade_status`` sysfs entry with boolean output value
97 * of ``0`` or ``1``, where ``0`` means no auto-downgrading was required during
98 * link training (which is the optimal scenario) and ``1`` means the device has
99 * auto-downgraded its link to PCIe Gen4 speed due to unstable Gen5 link.
100 *
101 * .. code-block:: shell
102 *
103 * $ cat /sys/bus/pci/devices/<bdf>/auto_link_downgrade_status
104 */
105
106 static ssize_t
107 auto_link_downgrade_capable_show(struct device *dev, struct device_attribute *attr, char *buf)
108 {
109 struct pci_dev *pdev = to_pci_dev(dev);
110 struct xe_device *xe = pdev_to_xe_device(pdev);
111 u32 cap, val;
112
113 xe_pm_runtime_get(xe);
114 val = xe_mmio_read32(xe_root_tile_mmio(xe), BMG_PCIE_CAP);
115 xe_pm_runtime_put(xe);
116
117 cap = REG_FIELD_GET(LINK_DOWNGRADE, val);
> 118 return sysfs_emit(buf, "%u\n", cap == DOWNGRADE_CAPABLE ? true : false);
119 }
120 static DEVICE_ATTR_ADMIN_RO(auto_link_downgrade_capable);
121
--
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