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Message-Id: <20250530-dp_mst_bindings-v2-2-f925464d32a8@oss.qualcomm.com>
Date: Fri, 30 May 2025 10:47:25 -0700
From: Jessica Zhang <jessica.zhang@....qualcomm.com>
To: Rob Clark <robdclark@...il.com>, Abhinav Kumar <quic_abhinavk@...cinc.com>,
Dmitry Baryshkov <lumag@...nel.org>, Sean Paul <sean@...rly.run>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Kuogee Hsieh <quic_khsieh@...cinc.com>,
Abel Vesa <abel.vesa@...aro.org>,
Bjorn Andersson <andersson@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Mahadevan <quic_mahap@...cinc.com>,
Krishna Manikandan <quic_mkrishn@...cinc.com>,
Konrad Dybcio <konradybcio@...nel.org>,
Danila Tikhonov <danila@...xyga.com>
Cc: linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
Yongxing Mou <quic_yongmou@...cinc.com>,
Jessica Zhang <jessica.zhang@....qualcomm.com>
Subject: [PATCH v2 2/5] dt-bindings: clock: Add SC7280 DISPCC DP pixel 1
clock binding
From: Abhinav Kumar <quic_abhinavk@...cinc.com>
Add DISP_CC_MDSS_DP_PIXEL1_* macros for SC7280
Signed-off-by: Abhinav Kumar <quic_abhinavk@...cinc.com>
Signed-off-by: Jessica Zhang <jessica.zhang@....qualcomm.com>
---
include/dt-bindings/clock/qcom,dispcc-sc7280.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/qcom,dispcc-sc7280.h b/include/dt-bindings/clock/qcom,dispcc-sc7280.h
index a4a692c20acf..25f736629593 100644
--- a/include/dt-bindings/clock/qcom,dispcc-sc7280.h
+++ b/include/dt-bindings/clock/qcom,dispcc-sc7280.h
@@ -48,6 +48,8 @@
#define DISP_CC_MDSS_VSYNC_CLK_SRC 38
#define DISP_CC_SLEEP_CLK 39
#define DISP_CC_XO_CLK 40
+#define DISP_CC_MDSS_DP_PIXEL1_CLK 41
+#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 42
/* DISP_CC power domains */
#define DISP_CC_MDSS_CORE_GDSC 0
--
2.49.0
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