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Message-ID: <20250530032252.3092502-1-dqfext@gmail.com>
Date: Fri, 30 May 2025 11:22:51 +0800
From: Qingfang Deng <dqfext@...il.com>
To: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Alexandre Ghiti <alex@...ti.fr>,
linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: [PATCH] riscv: use generic MMIO accessors
RISC-V IO just reads/writes the memory location directly, so remove
those __raw_read/write* definitions and use the generic accessors
instead.
The __io_reads_ins and __io_writes_outs macros are updated accordingly,
as they don't have access to the generic accessors.
Simplifies the code with no functional change.
Signed-off-by: Qingfang Deng <dqfext@...il.com>
---
arch/riscv/include/asm/io.h | 4 +--
arch/riscv/include/asm/mmio.h | 65 -----------------------------------
2 files changed, 2 insertions(+), 67 deletions(-)
diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index a0e51840b9db..6cee9d083d3c 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -68,7 +68,7 @@
ctype *buf = buffer; \
\
do { \
- ctype x = __raw_read ## len(addr); \
+ ctype x = *(const volatile ctype __force *)addr;\
*buf++ = x; \
} while (--count); \
} \
@@ -85,7 +85,7 @@
const ctype *buf = buffer; \
\
do { \
- __raw_write ## len(*buf++, addr); \
+ *(volatile ctype __force *)addr = *buf++; \
} while (--count); \
} \
afence; \
diff --git a/arch/riscv/include/asm/mmio.h b/arch/riscv/include/asm/mmio.h
index 06cadfd7a237..61286ee65f0b 100644
--- a/arch/riscv/include/asm/mmio.h
+++ b/arch/riscv/include/asm/mmio.h
@@ -15,71 +15,6 @@
#include <asm/fence.h>
#include <asm/mmiowb.h>
-/* Generic IO read/write. These perform native-endian accesses. */
-#define __raw_writeb __raw_writeb
-static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
-{
- asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr));
-}
-
-#define __raw_writew __raw_writew
-static inline void __raw_writew(u16 val, volatile void __iomem *addr)
-{
- asm volatile("sh %0, 0(%1)" : : "r" (val), "r" (addr));
-}
-
-#define __raw_writel __raw_writel
-static inline void __raw_writel(u32 val, volatile void __iomem *addr)
-{
- asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
-}
-
-#ifdef CONFIG_64BIT
-#define __raw_writeq __raw_writeq
-static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
-{
- asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr));
-}
-#endif
-
-#define __raw_readb __raw_readb
-static inline u8 __raw_readb(const volatile void __iomem *addr)
-{
- u8 val;
-
- asm volatile("lb %0, 0(%1)" : "=r" (val) : "r" (addr));
- return val;
-}
-
-#define __raw_readw __raw_readw
-static inline u16 __raw_readw(const volatile void __iomem *addr)
-{
- u16 val;
-
- asm volatile("lh %0, 0(%1)" : "=r" (val) : "r" (addr));
- return val;
-}
-
-#define __raw_readl __raw_readl
-static inline u32 __raw_readl(const volatile void __iomem *addr)
-{
- u32 val;
-
- asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
- return val;
-}
-
-#ifdef CONFIG_64BIT
-#define __raw_readq __raw_readq
-static inline u64 __raw_readq(const volatile void __iomem *addr)
-{
- u64 val;
-
- asm volatile("ld %0, 0(%1)" : "=r" (val) : "r" (addr));
- return val;
-}
-#endif
-
/*
* Unordered I/O memory access primitives. These are even more relaxed than
* the relaxed versions, as they don't even order accesses between successive
--
2.43.0
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