linux-kernel - [PATCH v2 2/3] arm64: dts: renesas: r8a779g0: Describe root port on R-Car V4H

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20250530225504.55042-2-marek.vasut+renesas@mailbox.org>
Date: Sat, 31 May 2025 00:53:20 +0200
From: Marek Vasut <marek.vasut+renesas@...lbox.org>
To: linux-arm-kernel@...ts.infradead.org
Cc: Marek Vasut <marek.vasut+renesas@...lbox.org>,
	Bartosz Golaszewski <brgl@...ev.pl>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	Conor Dooley <conor+dt@...nel.org>,
	Geert Uytterhoeven <geert+renesas@...der.be>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Magnus Damm <magnus.damm@...il.com>,
	Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
	Rob Herring <robh@...nel.org>,
	Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	linux-pci@...r.kernel.org,
	linux-renesas-soc@...r.kernel.org
Subject: [PATCH v2 2/3] arm64: dts: renesas: r8a779g0: Describe root port on R-Car V4H

Add node which describes the root port into PCIe controller DT node.
This can be used together with pwrctrl driver to control clock and
power supply to a PCIe slot. For example usage, refer to V4H Sparrow
Hawk board.

Signed-off-by: Marek Vasut <marek.vasut+renesas@...lbox.org>
---
Cc: Bartosz Golaszewski <brgl@...ev.pl>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>
Cc: Conor Dooley <conor+dt@...nel.org>
Cc: Geert Uytterhoeven <geert+renesas@...der.be>
Cc: Krzysztof Kozlowski <krzk+dt@...nel.org>
Cc: Magnus Damm <magnus.damm@...il.com>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Cc: Rob Herring <robh@...nel.org>
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>
Cc: devicetree@...r.kernel.org
Cc: linux-kernel@...r.kernel.org
Cc: linux-pci@...r.kernel.org
Cc: linux-renesas-soc@...r.kernel.org
---
V2: New patch
---
 arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index 6dbf05a559357..8d9ca30c299c9 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -798,6 +798,16 @@ pciec0: pcie@...d0000 {
 					<0 0 0 4 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;
 			snps,enable-cdm-check;
 			status = "disabled";
+
+			/* PCIe bridge, Root Port */
+			pciec0_rp: pci@0,0 {
+				#address-cells = <3>;
+				#size-cells = <2>;
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				compatible = "pciclass,0604";
+				device_type = "pci";
+				ranges;
+			};
 		};
 
 		pciec1: pcie@...d8000 {
@@ -835,6 +845,16 @@ pciec1: pcie@...d8000 {
 					<0 0 0 4 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
 			snps,enable-cdm-check;
 			status = "disabled";
+
+			/* PCIe bridge, Root Port */
+			pciec1_rp: pci@0,0 {
+				#address-cells = <3>;
+				#size-cells = <2>;
+				reg = <0x0 0x0 0x0 0x0 0x0>;
+				compatible = "pciclass,0604";
+				device_type = "pci";
+				ranges;
+			};
 		};
 
 		pciec0_ep: pcie-ep@...d0000 {
-- 
2.47.2