linux-kernel - [tip: perf/urgent] perf/x86/intel: Fix incorrect MSR index calculations in intel_pmu_config

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Message-ID: <174867991161.406.9289935407362158037.tip-bot2@tip-bot2>
Date: Sat, 31 May 2025 08:25:11 -0000
From: "tip-bot2 for Dapeng Mi" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: Dapeng Mi <dapeng1.mi@...ux.intel.com>, Ingo Molnar <mingo@...nel.org>,
 Kan Liang <kan.liang@...ux.intel.com>, Peter Zijlstra <peterz@...radead.org>,
 x86@...nel.org, linux-kernel@...r.kernel.org
Subject: [tip: perf/urgent] perf/x86/intel: Fix incorrect MSR index
 calculations in intel_pmu_config_acr()

The following commit has been merged into the perf/urgent branch of tip:

Commit-ID:     86aa94cd50b138be0dd872b0779fa3036e641881
Gitweb:        https://git.kernel.org/tip/86aa94cd50b138be0dd872b0779fa3036e641881
Author:        Dapeng Mi <dapeng1.mi@...ux.intel.com>
AuthorDate:    Thu, 29 May 2025 08:02:36 
Committer:     Ingo Molnar <mingo@...nel.org>
CommitterDate: Sat, 31 May 2025 10:05:16 +02:00

perf/x86/intel: Fix incorrect MSR index calculations in intel_pmu_config_acr()

The MSR offset calculations in intel_pmu_config_acr() are buggy.

To calculate fixed counter MSR addresses in intel_pmu_config_acr(),
the HW counter index "idx" is subtracted by INTEL_PMC_IDX_FIXED.

This leads to the ACR mask value of fixed counters to be incorrectly
saved to the positions of GP counters in acr_cfg_b[], e.g.

For fixed counter 0, its ACR counter mask should be saved to
acr_cfg_b[32], but it's saved to acr_cfg_b[0] incorrectly.

Fix this issue.

[ mingo: Clarified & improved the changelog. ]

Fixes: ec980e4facef ("perf/x86/intel: Support auto counter reload")
Signed-off-by: Dapeng Mi <dapeng1.mi@...ux.intel.com>
Signed-off-by: Ingo Molnar <mingo@...nel.org>
Reviewed-by: Kan Liang <kan.liang@...ux.intel.com>
Cc: Peter Zijlstra <peterz@...radead.org>
Link: https://lore.kernel.org/r/20250529080236.2552247-2-dapeng1.mi@linux.intel.com
---
 arch/x86/events/intel/core.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 4662833..741b229 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2900,6 +2900,7 @@ static void intel_pmu_config_acr(int idx, u64 mask, u32 reload)
 {
 	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
 	int msr_b, msr_c;
+	int msr_offset;
 
 	if (!mask && !cpuc->acr_cfg_b[idx])
 		return;
@@ -2907,19 +2908,20 @@ static void intel_pmu_config_acr(int idx, u64 mask, u32 reload)
 	if (idx < INTEL_PMC_IDX_FIXED) {
 		msr_b = MSR_IA32_PMC_V6_GP0_CFG_B;
 		msr_c = MSR_IA32_PMC_V6_GP0_CFG_C;
+		msr_offset = x86_pmu.addr_offset(idx, false);
 	} else {
 		msr_b = MSR_IA32_PMC_V6_FX0_CFG_B;
 		msr_c = MSR_IA32_PMC_V6_FX0_CFG_C;
-		idx -= INTEL_PMC_IDX_FIXED;
+		msr_offset = x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false);
 	}
 
 	if (cpuc->acr_cfg_b[idx] != mask) {
-		wrmsrl(msr_b + x86_pmu.addr_offset(idx, false), mask);
+		wrmsrl(msr_b + msr_offset, mask);
 		cpuc->acr_cfg_b[idx] = mask;
 	}
 	/* Only need to update the reload value when there is a valid config value. */
 	if (mask && cpuc->acr_cfg_c[idx] != reload) {
-		wrmsrl(msr_c + x86_pmu.addr_offset(idx, false), reload);
+		wrmsrl(msr_c + msr_offset, reload);
 		cpuc->acr_cfg_c[idx] = reload;
 	}
 }