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Message-ID: <e486d187-e869-98b5-a0cb-8bd463540312@linux.intel.com>
Date: Tue, 3 Jun 2025 12:21:46 +0300 (EEST)
From: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
To: Hans Zhang <18255117159@....com>
cc: lpieralisi@...nel.org, bhelgaas@...gle.com, 
    manivannan.sadhasivam@...aro.org, kw@...ux.com, cassel@...nel.org, 
    robh@...nel.org, jingoohan1@...il.com, linux-pci@...r.kernel.org, 
    LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v12 1/6] PCI: Introduce generic bus config read helper
 function

On Tue, 3 Jun 2025, Ilpo Järvinen wrote:

> On Thu, 15 May 2025, Hans Zhang wrote:
> 
> > The primary PCI config space accessors are tied to the size of the read
> > (byte/word/dword). Upcoming refactoring of PCI capability discovery logic
> > requires passing a config accessor function that must be able to perform
> > read with different sizes.
> > 
> > Add any size config space read accessor pci_bus_read_config() to allow
> > giving it as the config space accessor to the upcoming PCI capability
> > discovery macro.
> > 
> > Reconstructs the PCI function discovery logic to prepare for unified
> > configuration of access modes. No function changes are intended.
> > 
> > Signed-off-by: Hans Zhang <18255117159@....com>
> > ---
> > Changes since v9 ~ v11:
> > - None
> > 
> > Changes since v8:
> > - The new split is patch 1/6.
> > - The patch commit message were modified.
> > ---
> >  drivers/pci/access.c | 17 +++++++++++++++++
> >  drivers/pci/pci.h    |  2 ++
> >  2 files changed, 19 insertions(+)
> > 
> > diff --git a/drivers/pci/access.c b/drivers/pci/access.c
> > index b123da16b63b..603332658ab3 100644
> > --- a/drivers/pci/access.c
> > +++ b/drivers/pci/access.c
> > @@ -85,6 +85,23 @@ EXPORT_SYMBOL(pci_bus_write_config_byte);
> >  EXPORT_SYMBOL(pci_bus_write_config_word);
> >  EXPORT_SYMBOL(pci_bus_write_config_dword);
> >  
> > +int pci_bus_read_config(void *priv, unsigned int devfn, int where, u32 size,
> > +			u32 *val)
> > +{
> > +	struct pci_bus *bus = priv;
> > +	int ret;
> > +
> > +	if (size == 1)
> > +		ret = pci_bus_read_config_byte(bus, devfn, where, (u8 *)val);
> > +	else if (size == 2)
> > +		ret = pci_bus_read_config_word(bus, devfn, where, (u16 *)val);
> > +	else
> > +		ret = pci_bus_read_config_dword(bus, devfn, where, val);
> 
> Perhaps this should check also size == 4 and return 
> PCIBIOS_BAD_REGISTER_NUMBER in case size is wrong.
> 
> > +
> > +	return ret;

I'd also forgo ret variable and return directly.

> > +}
> > +EXPORT_SYMBOL_GPL(pci_bus_read_config);
> 
> Does this even need to be exported? Isn't the capability search always 
> built in?
> 
> >  int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
> >  			    int where, int size, u32 *val)
> >  {
> > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> > index b81e99cd4b62..5e1477d6e254 100644
> > --- a/drivers/pci/pci.h
> > +++ b/drivers/pci/pci.h
> > @@ -88,6 +88,8 @@ extern bool pci_early_dump;
> >  bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
> >  bool pcie_cap_has_lnkctl2(const struct pci_dev *dev);
> >  bool pcie_cap_has_rtctl(const struct pci_dev *dev);
> > +int pci_bus_read_config(void *priv, unsigned int devfn, int where, u32 size,
> > +			u32 *val);
> >  
> >  /* Functions internal to the PCI core code */
> >  
> > 
> 
> 

-- 
 i.

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