| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <CABymUCPqypTPh=Ao9PN44eq2_TXODhHd3EtSDeG+J0DcXQN6Eg@mail.gmail.com>
Date: Tue, 3 Jun 2025 22:37:37 +0800
From: Jun Nie <jun.nie@...aro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
Cc: Rob Clark <robdclark@...il.com>, Abhinav Kumar <quic_abhinavk@...cinc.com>,
Sean Paul <sean@...rly.run>, Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Jessica Zhang <quic_jesszhan@...cinc.com>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>, Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>, linux-arm-msm@...r.kernel.org,
dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v11 10/12] drm/msm/dpu: support SSPP assignment for
quad-pipe case
Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com> 于2025年6月3日周二 18:21写道：
>
> On Tue, Jun 03, 2025 at 03:10:09PM +0800, Jun Nie wrote:
> > Currently, SSPPs are assigned to a maximum of two pipes. However,
> > quad-pipe usage scenarios require four pipes and involve configuring
> > two stages. In quad-pipe case, the first two pipes share a set of
> > mixer configurations and enable multi-rect mode when certain
> > conditions are met. The same applies to the subsequent two pipes.
> >
> > Assign SSPPs to the pipes in each stage using a unified method and
> > to loop the stages accordingly.
> >
> > Signed-off-by: Jun Nie <jun.nie@...aro.org>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 148 +++++++++++++++++++-----------
> > 1 file changed, 94 insertions(+), 54 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > index 0bb153a71353ca9eaca138ebbee4cd699414771d..501b6a1bad4a1fee832f15efa7caec136a669da5 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> > @@ -961,6 +961,33 @@ static int dpu_plane_is_multirect_parallel_capable(struct dpu_hw_sspp *sspp,
> > dpu_plane_is_parallel_capable(pipe_cfg, fmt, max_linewidth);
> > }
> >
> > +static bool dpu_plane_get_single_pipe(struct dpu_plane_state *pstate,
> > + struct dpu_sw_pipe **single_pipe,
> > + struct dpu_sw_pipe_cfg **single_pipe_cfg,
> > + bool config_pipe)
>
> Could you please describe, what does this function do? Why is it
> returning the pipe or configuring a pipe?
It search all pipes. If there is only one valid pipe, return it via
pointer and function returns true.
If the config_pipe flag is set, multirect_index and multirect_mode are
also initialized. See below.
>
> > +{
> > + int i, valid_pipe = 0;
> > + struct dpu_sw_pipe *pipe;
> > +
> > + for (i = 0; i < PIPES_PER_PLANE; i++) {
> > + if (drm_rect_width(&pstate->pipe_cfg[i].src_rect) != 0) {
> > + valid_pipe++;
> > + if (valid_pipe > 1)
> > + return false;
> > + *single_pipe = &pstate->pipe[i];
> > + *single_pipe_cfg = &pstate->pipe_cfg[i];
> > + } else {
> > + if (!config_pipe)
> > + continue;
> > + pipe = &pstate->pipe[i];
> > + pipe->multirect_index = DPU_SSPP_RECT_SOLO;
> > + pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
> > + pipe->sspp = NULL;
> > + }
> > + }
> > +
> > + return true;
> > +}
> >
> > static int dpu_plane_atomic_check_sspp(struct drm_plane *plane,
> > struct drm_atomic_state *state,
> > @@ -1028,15 +1055,15 @@ static int dpu_plane_try_multirect_shared(struct dpu_plane_state *pstate,
> > const struct msm_format *fmt,
> > uint32_t max_linewidth)
> > {
> > - struct dpu_sw_pipe *pipe = &pstate->pipe[0];
> > - struct dpu_sw_pipe *r_pipe = &pstate->pipe[1];
> > - struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg[0];
> > - struct dpu_sw_pipe *prev_pipe = &prev_adjacent_pstate->pipe[0];
> > - struct dpu_sw_pipe_cfg *prev_pipe_cfg = &prev_adjacent_pstate->pipe_cfg[0];
> > + struct dpu_sw_pipe *pipe, *prev_pipe;
> > + struct dpu_sw_pipe_cfg *pipe_cfg, *prev_pipe_cfg;
> > const struct msm_format *prev_fmt = msm_framebuffer_format(prev_adjacent_pstate->base.fb);
> > u16 max_tile_height = 1;
> >
> > - if (prev_adjacent_pstate->pipe[1].sspp != NULL ||
> > + if (!dpu_plane_get_single_pipe(pstate, &pipe, &pipe_cfg, true))
> > + return false;
> > +
> > + if (!dpu_plane_get_single_pipe(prev_adjacent_pstate, &prev_pipe, &prev_pipe_cfg, false) ||
> > prev_pipe->multirect_mode != DPU_SSPP_MULTIRECT_NONE)
> > return false;
> >
> > @@ -1050,11 +1077,6 @@ static int dpu_plane_try_multirect_shared(struct dpu_plane_state *pstate,
> > if (MSM_FORMAT_IS_UBWC(prev_fmt))
> > max_tile_height = max(max_tile_height, prev_fmt->tile_height);
> >
> > - r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
> > - r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
> > -
> > - r_pipe->sspp = NULL;
> > -
Flag in dpu_plane_get_single_pipe() replace the initialization here.
> > if (dpu_plane_is_parallel_capable(pipe_cfg, fmt, max_linewidth) &&
> > dpu_plane_is_parallel_capable(prev_pipe_cfg, prev_fmt, max_linewidth) &&
> > (pipe_cfg->dst_rect.x1 >= prev_pipe_cfg->dst_rect.x2 ||
> > @@ -1183,6 +1205,51 @@ static int dpu_plane_virtual_atomic_check(struct drm_plane *plane,
> > return 0;
> > }
> >
> > +static int dpu_plane_try_multirect_in_stage(struct dpu_sw_pipe *pipe,
> > + struct dpu_sw_pipe_cfg *pipe_cfg,
> > + struct drm_plane_state *plane_state,
> > + struct dpu_global_state *global_state,
> > + struct drm_crtc *crtc,
> > + struct dpu_rm_sspp_requirements *reqs)
> > +{
> > + struct drm_plane *plane = plane_state->plane;
> > + struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
> > + struct dpu_plane *pdpu = to_dpu_plane(plane);
> > + struct dpu_sw_pipe *r_pipe = pipe + 1;
> > + struct dpu_sw_pipe_cfg *r_pipe_cfg = pipe_cfg + 1;
> > + int i;
> > +
> > + for (i = 0; i < PIPES_PER_STAGE; i++, pipe++, pipe_cfg++) {
> > + if (drm_rect_width(&pipe_cfg->src_rect) == 0)
> > + continue;
> > +
> > + pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, reqs);
> > + if (!pipe->sspp)
> > + return -ENODEV;
> > +
> > + /*
> > + * If current pipe is the first pipe in a stage, check
> > + * multi-rect opportunity for the 2nd pipe in the stage.
> > + * SSPP multi-rect mode cross stage is not supported.
> > + */
> > + if (!i &&
>
> Unroll the loop. I think I've asked a similar change in the review of
> the previous patch.
I had thought you want to abstract handling to stage into a dedicated function,
not aware you want to remove loop. Will do that in next version.
>
> > + drm_rect_width(&r_pipe_cfg->src_rect) != 0 &&
> > + dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg,
> > + pipe->sspp,
> > + msm_framebuffer_format(plane_state->fb),
> > + dpu_kms->catalog->caps->max_linewidth)) {
> > + goto stage_assinged;
> > + } else {
> > + /* multirect is not possible, use dedicated SSPP */
> > + pipe->multirect_index = DPU_SSPP_RECT_SOLO;
> > + pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
> > + }
> > + }
> > +
> > +stage_assinged:
> > + return 0;
> > +}
> > +
> > static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc,
> > struct dpu_global_state *global_state,
> > struct drm_atomic_state *state,
> > @@ -1195,11 +1262,9 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc,
> > struct dpu_rm_sspp_requirements reqs;
> > struct dpu_plane_state *pstate, *prev_adjacent_pstate;
> > struct dpu_sw_pipe *pipe;
> > - struct dpu_sw_pipe *r_pipe;
> > struct dpu_sw_pipe_cfg *pipe_cfg;
> > - struct dpu_sw_pipe_cfg *r_pipe_cfg;
> > const struct msm_format *fmt;
> > - int i;
> > + int i, stage_id, ret;
> >
> > if (plane_state->crtc)
> > crtc_state = drm_atomic_get_new_crtc_state(state,
> > @@ -1209,11 +1274,6 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc,
> > prev_adjacent_pstate = prev_adjacent_plane_state ?
> > to_dpu_plane_state(prev_adjacent_plane_state) : NULL;
> >
> > - pipe = &pstate->pipe[0];
> > - r_pipe = &pstate->pipe[1];
> > - pipe_cfg = &pstate->pipe_cfg[0];
> > - r_pipe_cfg = &pstate->pipe_cfg[1];
> > -
> > for (i = 0; i < PIPES_PER_PLANE; i++)
> > pstate->pipe[i].sspp = NULL;
> >
> > @@ -1227,44 +1287,24 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc,
> >
> > reqs.rot90 = drm_rotation_90_or_270(plane_state->rotation);
> >
> > - if (drm_rect_width(&r_pipe_cfg->src_rect) == 0) {
> > - if (!prev_adjacent_pstate ||
> > - !dpu_plane_try_multirect_shared(pstate, prev_adjacent_pstate, fmt,
> > - dpu_kms->catalog->caps->max_linewidth)) {
> > - pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs);
> > - if (!pipe->sspp)
> > - return -ENODEV;
> > -
> > - r_pipe->sspp = NULL;
> > -
> > - pipe->multirect_index = DPU_SSPP_RECT_SOLO;
> > - pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
> > -
> > - r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
> > - r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
> > - }
> > - } else {
> > - pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs);
> > - if (!pipe->sspp)
> > - return -ENODEV;
> > -
> > - if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg,
> > - pipe->sspp,
> > - msm_framebuffer_format(plane_state->fb),
> > - dpu_kms->catalog->caps->max_linewidth)) {
> > - /* multirect is not possible, use two SSPP blocks */
> > - r_pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs);
> > - if (!r_pipe->sspp)
> > - return -ENODEV;
> > -
> > - pipe->multirect_index = DPU_SSPP_RECT_SOLO;
> > - pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
> > + if (prev_adjacent_pstate &&
> > + dpu_plane_try_multirect_shared(pstate, prev_adjacent_pstate, fmt,
> > + dpu_kms->catalog->caps->max_linewidth)) {
>
> And this needs to take care of LMs. prev_adjacent_pstate should be
> per-stage, otherwise you can end up sharing the SSPPs between stages
> (which is not allowed).
Thanks for the reminder! I do miss the case here. Will get stage_id of 2
single pipes of 2 plane and check them to confirm whether SSPP can be shared.
>
> > + goto assigned;
> > + }
> >
> > - r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
> > - r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
> > - }
> > + for (stage_id = 0; stage_id < STAGES_PER_PLANE; stage_id++) {
> > + pipe = &pstate->pipe[stage_id * PIPES_PER_STAGE];
> > + pipe_cfg = &pstate->pipe_cfg[stage_id * PIPES_PER_STAGE];
> > + ret = dpu_plane_try_multirect_in_stage(pipe, pipe_cfg,
> > + plane_state,
> > + global_state,
> > + crtc, &reqs);
> > + if (ret)
> > + return ret;
> > }
> >
> > +assigned:
> > return dpu_plane_atomic_check_sspp(plane, state, crtc_state);
> > }
> >
> >
> > --
> > 2.34.1
> >
>
> --
> With best wishes
> Dmitry
Powered by blists - more mailing lists