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Message-Id: <20250604200301.1192096-1-Frank.Li@nxp.com>
Date: Wed, 4 Jun 2025 16:02:58 -0400
From: Frank Li <Frank.Li@....com>
To: Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
devicetree@...r.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS),
imx@...ts.linux.dev (open list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE),
linux-arm-kernel@...ts.infradead.org (moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE),
linux-kernel@...r.kernel.org (open list)
Cc: imx@...ts.linux.dev
Subject: [PATCH 1/4] arm64: dts: imx95-19x19-evk: add adc0 flexcan[1,2] i2c[2,3] uart5 spi3 and tpm3
Add adc0 flexcan[1,2] i2c[2,3] uart5 spi3 tpm3 netc_timer and related phys
regulators pinmux and related child nodes.
Signed-off-by: Frank Li <Frank.Li@....com>
---
.../boot/dts/freescale/imx95-19x19-evk.dts | 168 ++++++++++++++++++
1 file changed, 168 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
index 6886ea7666550..45015325fd47e 100644
--- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
@@ -77,6 +77,29 @@ linux_cma: linux,cma {
};
};
+ flexcan1_phy: can-phy0 {
+ compatible = "nxp,tjr1443";
+ #phy-cells = <0>;
+ max-bitrate = <1000000>;
+ enable-gpios = <&i2c6_pcal6416 6 GPIO_ACTIVE_HIGH>;
+ standby-gpios = <&i2c6_pcal6416 5 GPIO_ACTIVE_HIGH>;
+ };
+
+ flexcan2_phy: can-phy1 {
+ compatible = "nxp,tjr1443";
+ #phy-cells = <0>;
+ max-bitrate = <1000000>;
+ enable-gpios = <&i2c6_pcal6416 4 GPIO_ACTIVE_HIGH>;
+ standby-gpios = <&i2c6_pcal6416 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_vref_1v8: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "+V1.8_SW";
+ };
+
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
@@ -204,6 +227,11 @@ sound-wm8962 {
};
};
+&adc1 {
+ vref-supply = <®_vref_1v8>;
+ status = "okay";
+};
+
&enetc_port0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enetc0>;
@@ -212,6 +240,20 @@ &enetc_port0 {
status = "okay";
};
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ phys = <&flexcan1_phy>;
+ status = "disabled";
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ phys = <&flexcan2_phy>;
+ status = "okay";
+};
+
&flexspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi1>;
@@ -231,6 +273,38 @@ flash@0 {
};
};
+&lpi2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpi2c2>;
+ status = "okay";
+
+ adp5585: io-expander@34 {
+ compatible = "adi,adp5585-00", "adi,adp5585";
+ reg = <0x34>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-reserved-ranges = <5 1>;
+ #pwm-cells = <3>;
+ };
+};
+
+&lpi2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpi2c3>;
+ status = "okay";
+
+ i2c3_gpio_expander_20: gpio@20 {
+ compatible = "nxp,pcal6408";
+ #gpio-cells = <2>;
+ gpio-controller;
+ reg = <0x20>;
+ vcc-supply = <®_3p3v>;
+ };
+};
+
+
&lpi2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
@@ -378,6 +452,31 @@ &lpuart1 {
status = "okay";
};
+&lpuart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ status = "disabled";
+
+ bluetooth {
+ compatible = "nxp,88w8987-bt";
+ };
+};
+
+&lpspi7 {
+ num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpspi7>;
+ cs-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ spidev0: spi@0 {
+ reg = <0>;
+ compatible = "lwn,bk4-spi";
+ spi-max-frequency = <1000000>;
+ };
+};
+
+
&micfil {
#sound-dai-cells = <0>;
pinctrl-names = "default";
@@ -418,6 +517,10 @@ ethphy0: ethernet-phy@1 {
};
};
+&netc_timer {
+ status = "okay";
+};
+
&pcie0 {
pinctrl-0 = <&pinctrl_pcie0>;
pinctrl-names = "default";
@@ -484,6 +587,12 @@ &sai3 {
status = "okay";
};
+&tpm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tpm3>;
+ status = "okay";
+};
+
&usb2 {
dr_mode = "host";
disable-over-current;
@@ -588,6 +697,20 @@ IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e
>;
};
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e
+ IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e
+ IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e
+ >;
+ };
+
pinctrl_flexspi1: flexspi1grp {
fsl,pins = <
IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x3fe
@@ -628,6 +751,27 @@ IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x31e
>;
};
+ pinctrl_lpi2c1: lpi2c1grp {
+ fsl,pins = <
+ IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x40000b9e
+ IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c2: lpi2c2grp {
+ fsl,pins = <
+ IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e
+ IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c3: lpi2c3grp {
+ fsl,pins = <
+ IMX95_PAD_GPIO_IO00__LPI2C3_SDA 0x40000b9e
+ IMX95_PAD_GPIO_IO01__LPI2C3_SCL 0x40000b9e
+ >;
+ };
+
pinctrl_lpi2c4: lpi2c4grp {
fsl,pins = <
IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e
@@ -656,6 +800,15 @@ IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x40000b9e
>;
};
+ pinctrl_lpspi7: lpspi7grp {
+ fsl,pins = <
+ IMX95_PAD_GPIO_IO04__GPIO2_IO_BIT4 0x3fe
+ IMX95_PAD_GPIO_IO05__LPSPI7_SIN 0x3fe
+ IMX95_PAD_GPIO_IO06__LPSPI7_SOUT 0x3fe
+ IMX95_PAD_GPIO_IO07__LPSPI7_SCK 0x3fe
+ >;
+ };
+
pinctrl_pcie0: pcie0grp {
fsl,pins = <
IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x4000031e
@@ -716,6 +869,12 @@ IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x31e
>;
};
+ pinctrl_tpm3: tpm3grp {
+ fsl,pins = <
+ IMX95_PAD_GPIO_IO12__TPM3_CH2 0x51e
+ >;
+ };
+
pinctrl_tpm6: tpm6grp {
fsl,pins = <
IMX95_PAD_GPIO_IO19__TPM6_CH2 0x51e
@@ -729,6 +888,15 @@ IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e
>;
};
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
+ IMX95_PAD_DAP_TDI__LPUART5_RX 0x31e
+ IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
+ IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
--
2.34.1
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