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Message-ID: <66af3e62-83c7-4859-b8af-215098a825f0@lunn.ch>
Date: Wed, 4 Jun 2025 23:07:11 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Quentin Schulz <foss+kernel@...il.net>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Heiko Stuebner <heiko@...ech.de>,
Jakob Unterwurzacher <jakob.unterwurzacher@...rry.de>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
Quentin Schulz <quentin.schulz@...rry.de>
Subject: Re: [PATCH v3] arm64: dts: rockchip: support Ethernet Switch adapter
for RK3588 Jaguar
> +&gmac1 {
> + clock_in_out = "output";
> + phy-mode = "rgmii-id";
> + pinctrl-names = "default";
> + pinctrl-0 = <&gmac1_rx_bus2
> + &gmac1_tx_bus2
> + &gmac1_rgmii_clk
> + &gmac1_rgmii_bus
> + ð1_pins>;
> + rx_delay = <0x0>;
> + tx_delay = <0x0>;
> + status = "okay";
> +
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> + switch@5f {
> + compatible = "microchip,ksz9896";
> + reg = <0x5f>;
> + interrupt-parent = <&gpio3>;
> + interrupts = <RK_PB7 IRQ_TYPE_EDGE_FALLING>; /* ETH_INTRP_N */
> + pinctrl-0 = <ð_reset_n ð_intrp_n>;
> + pinctrl-names = "default";
> + reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; /* ETH_RESET */
> + microchip,synclko-disable; /* CLKO_25_125 only routed to TP1 */
> +
> + ethernet-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + lan1: port@0 {
> + reg = <0>;
> + label = "ETH1";
> + };
> +
> + lan2: port@1 {
> + reg = <1>;
> + label = "ETH2";
> + };
> +
> + lan3: port@2 {
> + reg = <2>;
> + label = "ETH3";
> + };
> +
> + lan4: port@3 {
> + reg = <3>;
> + label = "ETH4";
> + };
> +
> + port@5 {
> + reg = <5>;
> + ethernet = <&gmac1>;
> + label = "CPU";
> + phy-mode = "rgmii-id";
> + rx-internal-delay-ps = <2000>;
> + tx-internal-delay-ps = <2000>;
> +
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
For these bits only:
Reviewed-by: Andrew Lunn <andrew@...n.ch>
Andrew
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