linux-kernel - Re: [PATCH v3 5/5] phy: qcom: qmp-pcie: add x1e80100 qref supplies

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Message-ID: <aEBfV2M-ZqDF7aRz@hovoldconsulting.com>
Date: Wed, 4 Jun 2025 16:59:35 +0200
From: Johan Hovold <johan@...nel.org>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Cc: Qiang Yu <quic_qianyu@...cinc.com>,
	Wenbin Yao <quic_wenbyao@...cinc.com>, catalin.marinas@....com,
	will@...nel.org, linux-arm-kernel@...ts.infradead.org,
	andersson@...nel.org, konradybcio@...nel.org, robh@...nel.org,
	krzk+dt@...nel.org, conor+dt@...nel.org,
	linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, vkoul@...nel.org, kishon@...nel.org,
	sfr@...b.auug.org.au, linux-phy@...ts.infradead.org,
	krishna.chundru@....qualcomm.com, quic_vbadigan@...cinc.com,
	quic_mrana@...cinc.com, quic_cang@...cinc.com,
	Johan Hovold <johan+linaro@...nel.org>,
	Abel Vesa <abel.vesa@...aro.org>
Subject: Re: [PATCH v3 5/5] phy: qcom: qmp-pcie: add x1e80100 qref supplies

On Tue, May 27, 2025 at 12:50:21PM +0200, Konrad Dybcio wrote:
> On 5/26/25 3:47 PM, Johan Hovold wrote:
> > On Thu, May 22, 2025 at 10:03:18PM +0200, Konrad Dybcio wrote:
> >> On 5/8/25 11:45 AM, Johan Hovold wrote:
> >>> On Thu, May 08, 2025 at 04:50:30PM +0800, Qiang Yu wrote:
> >>>> On 5/8/2025 4:20 PM, Johan Hovold wrote:
> > 
> >>>>> This still looks wrong and you never replied to why these supplies
> >>>>> shouldn't be handled by the tcsr clock driver that supplies these
> >>>>> clocks:
> >>>>>
> >>>>> 	https://lore.kernel.org/lkml/aBHUmXx6N72_sCH9@hovoldconsulting.com/
> >>>
> >>>> Sorry, I thought Konrad had convinced you.
> >>>
> >>> IIRC, he just said you guys were told to add the QREF supply to the PHY.
> >>> That's not an argument.
> >>>
> >>>> If the TCSR driver manages these supplies, would it be possible for tscr
> >>>> driver to recognize when it needs to turn vdda-qref on or off for a
> >>>> specific PCIe port?
> >>>
> >>> Sure, just add a lookup table to the driver and enable the required
> >>> supplies when a ref clock is enabled.
> >>>
> >>> As I mentioned in the other thread, the T14s has the following QREF
> >>> supplies:
> >>>
> >>> 	
> >>> 	VDD_A_QREFS_1P2_A
> >>> 	VDD_A_QREFS_1P2_B
> >>>
> >>> 	VDD_A_QREFS_0P875_A
> >>> 	VDD_A_QREFS_0P875_B
> >>> 	VDD_A_QREFS_0P875_0
> >>> 	VDD_A_QREFS_0P875_2
> >>> 	VDD_A_QREFS_0P875_3
> >>>
> >>> and it's not clear how these maps to the various consumer ref clocks,
> >>> including the PCIe ones:
> >>>
> >>> 	#define TCSR_PCIE_2L_4_CLKREF_EN
> >>> 	#define TCSR_PCIE_2L_5_CLKREF_EN
> >>> 	#define TCSR_PCIE_8L_CLKREF_EN
> >>> 	#define TCSR_PCIE_4L_CLKREF_EN
> >>>
> >>> That mapping can be done by the TCSR clock driver (which would also take
> >>> care of the 1.2 V supplies).
> >>
> >> So we had an internal discussion about this and while it may work, it
> >> would only do so for some SoCs, and maybe only on the surface, as the
> >> wiring behind it is rather peculiar..
> > 
> > Care to expand on why it cannot be made to work generally?
> 
> "-ENODATA".. many connections are difficult to unambiguously decipher
> 
> > 
> > Also, what would the mapping of the above QREF supplies to PCIe PHYs
> > even look like?
> 
> I'm not sure I have a clear answer..

How would anyone know how to use a binding like this if you guys with
access to internal docs can't even answer how the QREF supplies maps to
the PHYs for a given SoC?

> >> Plus, not all QREF consumers have a clock expressed in TCSR as of
> >> right now.
> > 
> > Is that because there is no corresponding bit in the TCSR or simply
> > because it has not been described yet?
> 
> Unfortunately, the former.. Some IPs have a non-TCSR ref clock and
> some are presumably implicitly fed by BI_TCXO

I think you need to provide a lot more detail here so we can determine
how best best to proceed. We shouldn't accept made up PHY supplies
without a proper motivation just because that's how it's done
downstream.

Johan