lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <aEBvd8fIdjlTV53j@J2N7QTR9R3>
Date: Wed, 4 Jun 2025 17:08:23 +0100
From: Mark Rutland <mark.rutland@....com>
To: Peter Zijlstra <peterz@...radead.org>
Cc: Baisheng Gao <baisheng.gao@...soc.com>, Ingo Molnar <mingo@...hat.com>,
	Arnaldo Carvalho de Melo <acme@...nel.org>,
	Namhyung Kim <namhyung@...nel.org>,
	Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
	Jiri Olsa <jolsa@...nel.org>, Ian Rogers <irogers@...gle.com>,
	Adrian Hunter <adrian.hunter@...el.com>,
	"reviewer:PERFORMANCE EVENTS SUBSYSTEM" <kan.liang@...ux.intel.com>,
	"open list:PERFORMANCE EVENTS SUBSYSTEM" <linux-perf-users@...r.kernel.org>,
	"open list:PERFORMANCE EVENTS SUBSYSTEM" <linux-kernel@...r.kernel.org>,
	cixi.geng@...ux.dev, hao_hao.wang@...soc.com
Subject: Re: [PATCH] perf/core: Handling the race between exit_mmap and perf
 sample

On Wed, Jun 04, 2025 at 05:32:19PM +0200, Peter Zijlstra wrote:
> On Wed, Jun 04, 2025 at 03:55:01PM +0100, Mark Rutland wrote:
> 
> > I think we might need something in the perf core for cpu-bound events, assuming
> > those can also potentially make samples.
> > 
> > From a quick scan of perf_event_sample_format:

> > 	PERF_SAMPLE_DATA_PAGE_SIZE	// partial; doesn't check addr < TASK_SIZE
> > 	PERF_SAMPLE_CODE_PAGE_SIZE	// partial; doesn't check addr < TASK_SIZE
> 
> But does use init_mm when !mm, perf_get_page_size().

Yeah; think there might be a distinct issue (at least on arm64) where
it's possible to probe the depth of the kernel page tables, but that
might only be a problem on arm64 due to the separate TTBR0/TTBR1 tables
for the low/high halves.

I'll go take another look; that needn't block the rest of this.

[...]

> > 	PERF_SAMPLE_WEIGHT_STRUCT	// ???
> Safe, driver bits again.

Thanks for digging through the rest of these!

> > ... I think all the dodgy cases use mm somehow, so maybe the perf core
> > should check for current->mm?
> 
> This then... I suppose.

That looks good to me!

Mark.

> ---
> diff --git a/kernel/events/core.c b/kernel/events/core.c
> index f34c99f8ce8f..49944e4ec3e7 100644
> --- a/kernel/events/core.c
> +++ b/kernel/events/core.c
> @@ -7439,6 +7439,10 @@ perf_sample_ustack_size(u16 stack_size, u16 header_size,
>  	if (!regs)
>  		return 0;
>  
> +	/* No mm, no stack, no dump. */
> +	if (!current->mm)
> +		return 0;
> +
>  	/*
>  	 * Check if we fit in with the requested stack size into the:
>  	 * - TASK_SIZE
> @@ -8153,6 +8157,9 @@ perf_callchain(struct perf_event *event, struct pt_regs *regs)
>  	if (!kernel && !user)
>  		return &__empty_callchain;
>  
> +	if (!current->mm)
> +		user = false;
> +
>  	callchain = get_perf_callchain(regs, 0, kernel, user,
>  				       max_stack, crosstask, true);
>  	return callchain ?: &__empty_callchain;

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ