linux-kernel - Re: [PATCH v1] iommu/vt-d: Remove the redundant logic in first_level_by

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Message-ID: <d30b70da-d06e-4d96-b110-1459533e2943@gmail.com>
Date: Thu, 5 Jun 2025 11:33:56 +0800
From: Ethan Zhao <etzhao1900@...il.com>
To: "Wang, Wei W" <wei.w.wang@...el.com>, "Tian, Kevin"
 <kevin.tian@...el.com>, Ethan Zhao <haifeng.zhao@...ux.intel.com>,
 "baolu.lu@...ux.intel.com" <baolu.lu@...ux.intel.com>,
 "Liu, Yi L" <yi.l.liu@...el.com>, "dwmw2@...radead.org"
 <dwmw2@...radead.org>, "jroedel@...e.de" <jroedel@...e.de>,
 "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
 "iommu@...ts.linux.dev" <iommu@...ts.linux.dev>
Subject: Re: [PATCH v1] iommu/vt-d: Remove the redundant logic in
 first_level_by_default()



On 6/5/2025 9:04 AM, Wang, Wei W wrote:
> On Wednesday, June 4, 2025 3:26 PM, Ethan Zhao wrote:
>> On 5/29/2025 2:11 PM, Tian, Kevin wrote:
>>>> From: Ethan Zhao <haifeng.zhao@...ux.intel.com>
>>>> Sent: Thursday, May 29, 2025 1:48 PM
>>>>
>>>> 在 2025/5/23 16:10, Wei Wang 写道:
>>>>> This original implementation included redundant logic to determine
>>>> whether
>>>>> first-stage translation should be used by default. Simplify it and
>>>>> preserve the original behavior:
>>>>> - Returns false in legacy mode (no scalable mode support).
>>>>> - Defaults to first-level translation when both FLTS and SLTS are
>>>>>      supported.
>>>>>
>>>>> Signed-off-by: Wei Wang <wei.w.wang@...el.com>
>>>>> ---
>>>>>     drivers/iommu/intel/iommu.c | 10 +---------
>>>>>     1 file changed, 1 insertion(+), 9 deletions(-)
>>>>>
>>>>> diff --git a/drivers/iommu/intel/iommu.c
>>>>> b/drivers/iommu/intel/iommu.c index cb0b993bebb4..228da47ab7cd
>>>>> 100644
>>>>> --- a/drivers/iommu/intel/iommu.c
>>>>> +++ b/drivers/iommu/intel/iommu.c
>>>>> @@ -1366,15 +1366,7 @@ static void free_dmar_iommu(struct
>>>> intel_iommu *iommu)
>>>>>      */
>>>>>     static bool first_level_by_default(struct intel_iommu *iommu)
>>>>>     {
>>>>> -	/* Only SL is available in legacy mode */
>>>>> -	if (!sm_supported(iommu))
>>>>> -		return false;
>>>>> -
>>>>> -	/* Only level (either FL or SL) is available, just use it */
>>>>> -	if (ecap_flts(iommu->ecap) ^ ecap_slts(iommu->ecap))
>>>>> -		return ecap_flts(iommu->ecap);
>>>>> -
>>>>> -	return true;
>>>>
>>>> The function works like a digital circurt has 3 single bit inputs
>>>> sm, flts, slts and one bit output ret.
>>>>
>>>> so the true value table of the orignal function looks like
>>>>
>>>>       sm   flts   slts    ret
>>>> a   0     x     x      false
>>>> b   1     1     0      true
>>>> c   1     0     1      false
>>>> d   1     1     1      true
>>>> e   1     0     0      true
>>>
>>> 'e' is actually wrong. We should not return true when the 1st level
>>> cap doesn't exist.
>>
>> If so, this patch should mention it fixes such case with fix tag, not
>>    "removing the redundant logic with the same behavior".
>>
> 
> Probably not a fix (just code improvement). Your 'e' above is not possible
> from the hardware side, and the old implementation doesn't have it too.
> 
Is there any items in Intel VT-d spec to say "It is impossible to have 
both flts and slts to false" or you design code under an assumption that 
hardware always works perfect ?

You made an assumption that the hardware never would reach there and 
then got a conclusion 'e' doesn't exist ?


Thanks,
Ethan
> 
>>>
>>>>
>>>>> +	return sm_supported(iommu) && ecap_flts(iommu->ecap);
>>>>
>>>> And the true value table of this new one looks like
>>>>
>>>>       sm  flts slts    ret
>>>>
>>>> f   1     1     x      true
>>>> g   1     0     x      false
>>>>
>>>> h   0     1     x      false
>>>> i    0     0     x      false
>>>
>>> so this table is correct.
>