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Message-ID: <20250605192356.82250-18-darwi@linutronix.de>
Date: Thu, 5 Jun 2025 21:23:46 +0200
From: "Ahmed S. Darwish" <darwi@...utronix.de>
To: Ingo Molnar <mingo@...hat.com>,
Borislav Petkov <bp@...en8.de>,
Dave Hansen <dave.hansen@...ux.intel.com>
Cc: Thomas Gleixner <tglx@...utronix.de>,
Andrew Cooper <andrew.cooper3@...rix.com>,
"H. Peter Anvin" <hpa@...or.com>,
Peter Zijlstra <peterz@...radead.org>,
Sean Christopherson <seanjc@...gle.com>,
Sohil Mehta <sohil.mehta@...el.com>,
Ard Biesheuvel <ardb@...nel.org>,
John Ogness <john.ogness@...utronix.de>,
x86@...nel.org,
x86-cpuid@...ts.linux.dev,
LKML <linux-kernel@...r.kernel.org>,
"Ahmed S. Darwish" <darwi@...utronix.de>
Subject: [PATCH v2 17/27] x86/cpuid: Remove direct CPUID(0x2) query API
All call sites at x86/cpu and x86/cacheinfo has been switched from direct
CPUID(0x2) access to parsed CPUID access. Remove the direct CPUID(0x2)
query APIs at <asm/cpuid/api.h>:
cpuid_leaf_0x2()
for_each_cpuid_0x2_desc()
Rename the iterator macro:
for_each_parsed_cpuid_0x2_desc()
back to:
for_each_cpuid_0x2_desc()
since the "for_each_parsed_.." name and was just chosen to accommodate
the transition from direct CPUID(0x2) access to parsed access.
Signed-off-by: Ahmed S. Darwish <darwi@...utronix.de>
---
arch/x86/include/asm/cpuid/api.h | 69 +-------------------------------
arch/x86/kernel/cpu/cacheinfo.c | 2 +-
arch/x86/kernel/cpu/intel.c | 2 +-
3 files changed, 4 insertions(+), 69 deletions(-)
diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/api.h
index 7ee6b4443333..82d36d210930 100644
--- a/arch/x86/include/asm/cpuid/api.h
+++ b/arch/x86/include/asm/cpuid/api.h
@@ -216,73 +216,8 @@ static inline u32 cpuid_base_hypervisor(const char *sig, u32 leaves)
* CPUID(0x2) parsing:
*/
-/**
- * cpuid_leaf_0x2() - Return sanitized CPUID(0x2) register output
- * @regs: Output parameter
- *
- * Query CPUID(0x2) and store its output in @regs. Force set any
- * invalid 1-byte descriptor returned by the hardware to zero (the NULL
- * cache/TLB descriptor) before returning it to the caller.
- *
- * Use for_each_cpuid_0x2_desc() to iterate over the register output in
- * parsed form.
- */
-static inline void cpuid_leaf_0x2(union leaf_0x2_regs *regs)
-{
- cpuid_read(0x2, regs);
-
- /*
- * All Intel CPUs must report an iteration count of 1. In case
- * of bogus hardware, treat all returned descriptors as NULL.
- */
- if (regs->desc[0] != 0x01) {
- for (int i = 0; i < 4; i++)
- regs->regv[i] = 0;
- return;
- }
-
- /*
- * The most significant bit (MSB) of each register must be clear.
- * If a register is invalid, replace its descriptors with NULL.
- */
- for (int i = 0; i < 4; i++) {
- if (regs->reg[i].invalid)
- regs->regv[i] = 0;
- }
-}
-
/**
* for_each_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descriptors
- * @_regs: CPUID(0x2) register output, as returned by cpuid_leaf_0x2()
- * @_ptr: u8 pointer, for macro internal use only
- * @_desc: Pointer to the parsed CPUID(0x2) descriptor at each iteration
- *
- * Loop over the 1-byte descriptors in the passed CPUID(0x2) output registers
- * @_regs. Provide the parsed information for each descriptor through @_desc.
- *
- * To handle cache-specific descriptors, switch on @_desc->c_type. For TLB
- * descriptors, switch on @_desc->t_type.
- *
- * Example usage for cache descriptors::
- *
- * const struct leaf_0x2_table *desc;
- * union leaf_0x2_regs regs;
- * u8 *ptr;
- *
- * cpuid_leaf_0x2(®s);
- * for_each_cpuid_0x2_desc(regs, ptr, desc) {
- * switch (desc->c_type) {
- * ...
- * }
- * }
- */
-#define for_each_cpuid_0x2_desc(_regs, _ptr, _desc) \
- for (_ptr = &(_regs).desc[1]; \
- _ptr < &(_regs).desc[16] && (_desc = &cpuid_0x2_table[*_ptr]); \
- _ptr++)
-
-/**
- * for_each_parsed_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descriptors
* @_regs: Leaf 0x2 register output, as returned by cpuid_leaf_regs()
* @_ptr: u8 pointer, for macro internal use only
* @_desc: Pointer to parsed descriptor information at each iteration
@@ -304,13 +239,13 @@ static inline void cpuid_leaf_0x2(union leaf_0x2_regs *regs)
* // Handle error
* }
*
- * for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) {
+ * for_each_cpuid_0x2_desc(regs, ptr, desc) {
* switch (desc->c_type) {
* ...
* }
* }
*/
-#define for_each_parsed_cpuid_0x2_desc(_regs, _ptr, _desc) \
+#define for_each_cpuid_0x2_desc(_regs, _ptr, _desc) \
for (({ static_assert(sizeof(*_regs) == sizeof(union leaf_0x2_regs)); }), \
_ptr = &((union leaf_0x2_regs *)(_regs))->desc[1]; \
_ptr < &((union leaf_0x2_regs *)(_regs))->desc[16] && (_desc = &cpuid_0x2_table[*_ptr]);\
diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index 39cd6db4f702..f837ccdec116 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -389,7 +389,7 @@ static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c)
if (!regs)
return;
- for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) {
+ for_each_cpuid_0x2_desc(regs, ptr, desc) {
switch (desc->c_type) {
case CACHE_L1_INST: l1i += desc->c_size; break;
case CACHE_L1_DATA: l1d += desc->c_size; break;
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 5eab9135b144..06c249110c8b 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -717,7 +717,7 @@ static void intel_detect_tlb(struct cpuinfo_x86 *c)
if (!regs)
return;
- for_each_parsed_cpuid_0x2_desc(regs, ptr, desc)
+ for_each_cpuid_0x2_desc(regs, ptr, desc)
intel_tlb_lookup(desc);
}
--
2.49.0
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