linux-kernel - Re: [net-next RFC PATCH 1/2] dt-bindings: net: Document support for Airoha AN7583 MDIO Controller

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <20250605195225.GA3119975-robh@kernel.org>
Date: Thu, 5 Jun 2025 14:52:25 -0500
From: Rob Herring <robh@...nel.org>
To: Christian Marangi <ansuelsmth@...il.com>
Cc: Andrew Lunn <andrew+netdev@...n.ch>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Heiner Kallweit <hkallweit1@...il.com>,
	Russell King <linux@...linux.org.uk>,
	Philipp Zabel <p.zabel@...gutronix.de>, netdev@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [net-next RFC PATCH 1/2] dt-bindings: net: Document support for
 Airoha AN7583 MDIO Controller

On Tue, May 27, 2025 at 11:34:42PM +0200, Christian Marangi wrote:
> Airoha AN7583 SoC have 3 different MDIO Controller. One comes from
> the intergated Switch based on MT7530. The other 2 live under the SCU
> register and expose 2 dedicated MDIO controller.
> 
> Document the schema that expose the 2 dedicated MDIO controller.
> Each MDIO controller can be independently reset with the SoC reset line.
> 
> Signed-off-by: Christian Marangi <ansuelsmth@...il.com>
> ---
>  .../bindings/net/airoha,an7583-mdio.yaml      | 78 +++++++++++++++++++
>  1 file changed, 78 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/net/airoha,an7583-mdio.yaml
> 
> diff --git a/Documentation/devicetree/bindings/net/airoha,an7583-mdio.yaml b/Documentation/devicetree/bindings/net/airoha,an7583-mdio.yaml
> new file mode 100644
> index 000000000000..2375f1bf85a2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/airoha,an7583-mdio.yaml
> @@ -0,0 +1,78 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/airoha,an7583-mdio.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Airoha AN7583 Dedicated MDIO Controller
> +
> +maintainers:
> +  - Christian Marangi <ansuelsmth@...il.com>
> +
> +description:
> +  Airoha AN7583 SoC have 3 different MDIO Controller.
> +
> +  One comes from the intergated Switch based on MT7530.
> +
> +  The other 2 (that this schema describe) live under the SCU
> +  register supporting both C22 and C45 PHYs.
> +
> +properties:
> +  compatible:
> +    const: airoha,an7583-mdio
> +

No registers? Looks to me like this middle node should go and the SCU 
node should have 2 mdio child nodes at 0xc8 and 0xcc.

It looks like you'll need to define the speed mode bit location somehow 
as well.

> +  "#address-cells":
> +    const: 1
> +
> +  "#size-cells":
> +    const: 0
> +
> +patternProperties:
> +  '^mdio(-(bus|external))@[0-1]$':

Just '^mdio@[0-1]$'

If you need to distinguish external or something, use compatible or 
something.

> +    type: object
> +
> +    $ref: mdio.yaml#
> +
> +    properties:
> +      reg:
> +        minimum: 0
> +        maximum: 1
> +
> +      resets:
> +        maxItems: 1
> +
> +    required:
> +      - reg
> +
> +    unevaluatedProperties: false
> +
> +required:
> +  - compatible
> +  - "#address-cells"
> +  - "#size-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    mdio-controller {
> +        compatible = "airoha,an7583-mdio";
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +
> +        mdio-bus@0 {
> +            reg = <0>;
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +
> +            ethernet-phy@1f {
> +                reg = <31>;
> +            };
> +        };
> +
> +        mdio-bus@1 {
> +            reg = <1>;
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +        };
> +    };
> -- 
> 2.48.1
>