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Message-ID: <aEH6kpXStLc0dWZq@shikoro>
Date: Thu, 5 Jun 2025 22:14:10 +0200
From: Wolfram Sang <wsa+renesas@...g-engineering.com>
To: Frank Li <Frank.li@....com>
Cc: Jorge Marques <jorge.marques@...log.com>,
Alexandre Belloni <alexandre.belloni@...tlin.com>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, linux-i3c@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] i3c: master: Add driver for Analog Devices I3C
Controller IP
> > +static void adi_i3c_master_wr_to_tx_fifo(struct adi_i3c_master *master,
> > + const u8 *bytes, int nbytes)
> > +{
> > + writesl(master->regs + REG_SDO_FIFO, bytes, nbytes / 4);
> > + if (nbytes & 3) {
> > + u32 tmp = 0;
> > +
> > + memcpy(&tmp, bytes + (nbytes & ~3), nbytes & 3);
>
> ALIGN_DOWN(bytes, 4)?
>
> Do you need conside big/little endian to trim down data?
The driver uses the same code for reading/writing the FIFO as the
Designware and Cadence driver. The Renesas driver I am working on has
also the same pattern. Time for a helper function maybe
i3c_{read|write}l_to_fifo(register, data, length);
?
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