| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20250605132754.1771368-5-john.ernberg@actia.se>
Date: Thu, 5 Jun 2025 13:28:02 +0000
From: John Ernberg <john.ernberg@...ia.se>
To: Horia Geantă <horia.geanta@....com>, Pankaj Gupta
<pankaj.gupta@....com>, Gaurav Jain <gaurav.jain@....com>, Herbert Xu
<herbert@...dor.apana.org.au>, "David S . Miller" <davem@...emloft.net>, "Rob
Herring" <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, "Conor
Dooley" <conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>, Sascha Hauer
<s.hauer@...gutronix.de>
CC: Frank Li <Frank.li@....com>, Pengutronix Kernel Team
<kernel@...gutronix.de>, Fabio Estevam <festevam@...il.com>,
"linux-crypto@...r.kernel.org" <linux-crypto@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"imx@...ts.linux.dev" <imx@...ts.linux.dev>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>, John Ernberg <john.ernberg@...ia.se>
Subject: [PATCH v4 4/4] arm64: dts: freescale: imx8qxp/imx8qm: Add CAAM
support
From: Horia Geantă <horia.geanta@....com>
The iMX8QXP and iMX8QM have a CAAM (Cryptographic Acceleration and
Assurance Module) like many other iMXs.
Add the definitions for it.
Job Rings 0 and 1 are bound to the SECO (Security Controller) ARM core
and are not exposed outside it. There's no point to define them in the
bindings as they cannot be used outside the SECO.
Signed-off-by: Horia Geantă <horia.geanta@....com>
Signed-off-by: John Ernberg <john.ernberg@...ia.se>
---
Imported from NXP tree, trimmed down and fixed the dtbs_check warnings.
Constrained the ranges to the needed ones.
Changed the commit message.
Original here: https://github.com/nxp-imx/linux-imx/commit/699e54b386cb9b53def401798d0a4e646105583d
---
v4:
- Drop [ ] rework detailing from commit log. (Frank Li)
- Add an override dtsi to change the compatibles on QXP due to changes in
3/4. (Frank Li)
v3:
- no changes
v2:
- Use new compatibles introduced in 3/4 (Frank Li)
---
.../boot/dts/freescale/imx8-ss-security.dtsi | 38 +++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8qm.dtsi | 1 +
.../dts/freescale/imx8qxp-ss-security.dtsi | 16 ++++++++
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 2 +
4 files changed, 57 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi
create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-security.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi
new file mode 100644
index 000000000000..9ecabb2d03e9
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+security_subsys: bus@...00000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x31400000 0x0 0x31400000 0x90000>;
+
+ crypto: crypto@...00000 {
+ compatible = "fsl,imx8qm-caam", "fsl,sec-v4.0";
+ reg = <0x31400000 0x90000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x31400000 0x90000>;
+ fsl,sec-era = <9>;
+ power-domains = <&pd IMX_SC_R_CAAM_JR2>;
+
+ sec_jr2: jr@...00 {
+ compatible = "fsl,imx8qm-job-ring", "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd IMX_SC_R_CAAM_JR2>;
+ };
+
+ sec_jr3: jr@...00 {
+ compatible = "fsl,imx8qm-job-ring", "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&pd IMX_SC_R_CAAM_JR3>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index 6fa31bc9ece8..6df018643f20 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -612,6 +612,7 @@ vpu_dsp: dsp@...e8000 {
};
/* sorted in register address */
+ #include "imx8-ss-security.dtsi"
#include "imx8-ss-cm41.dtsi"
#include "imx8-ss-audio.dtsi"
#include "imx8-ss-vpu.dtsi"
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-security.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-security.dtsi
new file mode 100644
index 000000000000..15f1239dab24
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-security.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 Actia Nordic AB
+ */
+
+&crypto {
+ compatible = "fsl,imx8qxp-caam", "fsl,sec-v4.0";
+};
+
+&sec_jr2 {
+ compatible = "fsl,imx8qxp-job-ring", "fsl,sec-v4.0-job-ring";
+};
+
+&sec_jr3 {
+ compatible = "fsl,imx8qxp-job-ring", "fsl,sec-v4.0-job-ring";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 05138326f0a5..e2e799cc294c 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -321,6 +321,7 @@ map0 {
/* sorted in register address */
#include "imx8-ss-img.dtsi"
#include "imx8-ss-vpu.dtsi"
+ #include "imx8-ss-security.dtsi"
#include "imx8-ss-cm40.dtsi"
#include "imx8-ss-gpu0.dtsi"
#include "imx8-ss-adma.dtsi"
@@ -332,6 +333,7 @@ map0 {
#include "imx8qxp-ss-img.dtsi"
#include "imx8qxp-ss-vpu.dtsi"
+#include "imx8qxp-ss-security.dtsi"
#include "imx8qxp-ss-adma.dtsi"
#include "imx8qxp-ss-conn.dtsi"
#include "imx8qxp-ss-lsio.dtsi"
--
2.49.0
Powered by blists - more mailing lists