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Message-ID: <CALWfF7+BS1jHVrfNC9=OL0vcNoNqeXYBAwF3ueb1xVpfGf0s2A@mail.gmail.com>
Date: Thu, 5 Jun 2025 20:08:29 -0500
From: Jimmy Hon <honyuenkwun@...il.com>
To: Joseph Kogut <joseph.kogut@...il.com>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Heiko Stuebner <heiko@...ech.de>, devicetree@...r.kernel.org,
linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
Steve deRosier <derosier@...-sierra.com>
Subject: Re: [PATCH v4 3/3] arm64: dts: rockchip: Add support for CM5 IO carrier
On Thu, Jun 5, 2025 at 6:12 PM Joseph Kogut <joseph.kogut@...il.com> wrote:
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts
> new file mode 100644
> index 0000000000000000000000000000000000000000..6bdb38464820278fc94e0ceb893e204df33c0381
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts
> @@ -0,0 +1,454 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2025 Joseph Kogut <joseph.kogut@...il.com>
> + */
> +
> +/*
> + * CM5 IO board data sheet
> + * https://dl.radxa.com/cm5/v2200/radxa_cm5_io_v2200_schematic.pdf
> + */
> +
> +/dts-v1/;
> +#include "rk3588s.dtsi"
> +#include "rk3588s-radxa-cm5.dtsi"
> +
> +/ {
> + model = "Radxa Compute Module 5 (CM5) IO Board";
> + compatible = "radxa,cm5-io", "radxa,cm5", "rockchip,rk3588s";
> +
> + chosen {
> + stdout-path = "serial2:1500000n8";
> + };
> +
> + hdmi-con {
> + compatible = "hdmi-connector";
> + type = "a";
> +
> + port {
> + hdmi_con_in: endpoint {
> + remote-endpoint = <&hdmi0_out_con>;
> + };
> + };
> + };
> +
> + vcc12v_dcin: regulator-12v0-vcc-dcin {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc12v_dcin";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <12000000>;
> + regulator-max-microvolt = <12000000>;
> + };
> +
> + vcc5v0_host: vcc5v0-host-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc5v0_host";
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + enable-active-high;
> + gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&vcc5v0_host_en>;
> + vin-supply = <&vcc5v0_sys>;
> + };
> +
> + vcc5v0_sys: regulator-5v0-sys {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc5v0_sys";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + vin-supply = <&vcc12v_dcin>;
> + };
> +
> + vbus5v0_typec: vbus5v0-typec {
> + compatible = "regulator-fixed";
> + regulator-name = "vbus5v0_typec";
> + gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&vbus5v0_typec_en>;
> + enable-active-high;
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + vin-supply = <&vcc5v0_sys>;
> + };
> +
> + vcc3v3_pcie: regulator-3v3-vcc-pcie {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc3v3_pcie2x1l0";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + enable-active-high;
> + regulator-boot-on;
> + regulator-always-on;
> + gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
> + startup-delay-us = <50000>;
> + vin-supply = <&vcc5v0_sys>;
> + };
> +
> + vcc_3v3_s0: pldo-reg4 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc_3v3_s0";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-ramp-delay = <12500>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +};
> +
> +&combphy0_ps {
> + status = "okay";
> +};
> +
> +&combphy2_psu {
> + status = "okay";
> +};
> +
If you do end up moving the gmac1 enablement to the board, you should
also add an ethernet0 alias at the board level. Mainline does not
define the ethernet0 and ethernet1 aliases at the SoC level, like the
rockchip BSP kernel does (since not all boards will use gmac0 and
gmac1).
> +&hdmi0_in {
> + hdmi0_in_vp0: endpoint {
> + remote-endpoint = <&vp0_out_hdmi0>;
> + };
> +};
> +
> +&hdmi0_out {
> + hdmi0_out_con: endpoint {
> + remote-endpoint = <&hdmi_con_in>;
> + };
> +};
> +
> +&hdptxphy0 {
> + status = "okay";
> +};
You could also enable hdmi0_sound and i2s5_8ch. It's enabled in the
Radxa BSP kernel.
> +
> +&i2c6 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c6m3_xfer>;
> + status = "okay";
> +
> + fusb302: usb-typec@22 {
> + compatible = "fcs,fusb302";
> + reg = <0x22>;
> + interrupt-parent = <&gpio0>;
> + interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&usbc0_int>;
> + vbus-supply = <&vbus5v0_typec>;
> +
> + connector {
> + compatible = "usb-c-connector";
> + data-role = "dual";
> + label = "USB-C";
> + power-role = "dual";
> + try-power-role = "sink";
> + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
> + sink-pdos = <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
> + op-sink-microwatt = <1000000>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + usbc0_orientation_switch: endpoint {
> + remote-endpoint = <&usbdp_phy0_orientation_switch>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + usbc0_role_switch: endpoint {
> + remote-endpoint = <&usb_host0_xhci_role_switch>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + usbc0_dp_altmode_mux: endpoint {
> + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
> + };
> + };
> + };
> + };
> + };
> +};
> +
> +&pcie2x1l2 {
> + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
> + vpcie3v3-supply = <&vcc3v3_pcie>;
> + status = "okay";
> +};
> +
> +&pinctrl {
> + fusb302 {
> + vbus5v0_typec_en: vbus5v0-typec-en {
> + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> +
> + usbc0_int: usbc0-int {
> + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
> + };
> + };
> +
> + usb {
> + vcc5v0_host_en: vcc5v0-host-en {
> + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +};
> +
> +&sdhci {
> + status = "okay";
> +};
This is already enabled at the SoM dtsi.
> +
> +&sdmmc {
> + bus-width = <4>;
> + cap-mmc-highspeed;
> + cap-sd-highspeed;
> + disable-wp;
> + max-frequency = <200000000>;
> + no-sdio;
> + no-mmc;
> + sd-uhs-sdr104;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>;
> + vmmc-supply = <&vcc_3v3_s3>;
> + vqmmc-supply = <&vccio_sd_s0>;
> + status = "okay";
> +};
> +
> +&spi2 {
> + assigned-clocks = <&cru CLK_SPI2>;
> + assigned-clock-rates = <200000000>;
> + num-cs = <1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
> + status = "okay";
> +
> + pmic@0 {
> + compatible = "rockchip,rk806";
> + reg = <0x0>;
> + interrupt-parent = <&gpio0>;
> + interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
> + <&rk806_dvs2_null>, <&rk806_dvs3_null>;
> + spi-max-frequency = <1000000>;
> + system-power-controller;
> +
> + vcc1-supply = <&vcc5v0_sys>;
> + vcc2-supply = <&vcc5v0_sys>;
> + vcc3-supply = <&vcc5v0_sys>;
> + vcc4-supply = <&vcc5v0_sys>;
> + vcc5-supply = <&vcc5v0_sys>;
> + vcc6-supply = <&vcc5v0_sys>;
> + vcc7-supply = <&vcc5v0_sys>;
> + vcc8-supply = <&vcc5v0_sys>;
> + vcc9-supply = <&vcc5v0_sys>;
> + vcc10-supply = <&vcc5v0_sys>;
> + vcc11-supply = <&vcc_2v0_pldo_s3>;
> + vcc12-supply = <&vcc5v0_sys>;
> + vcc13-supply = <&vdd2_ddr_s3>;
> + vcc14-supply = <&vdd2_ddr_s3>;
> + vcca-supply = <&vcc5v0_sys>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + rk806_dvs1_null: dvs1-null-pins {
> + pins = "gpio_pwrctrl1";
> + function = "pin_fun0";
> + };
> +
> + rk806_dvs2_null: dvs2-null-pins {
> + pins = "gpio_pwrctrl2";
> + function = "pin_fun0";
> + };
> +
> + rk806_dvs3_null: dvs3-null-pins {
> + pins = "gpio_pwrctrl3";
> + function = "pin_fun0";
> + };
> +
> + regulators {
> + vdd_gpu_s0: dcdc-reg1 {
> + regulator-name = "vdd_gpu_s0";
> + regulator-boot-on;
> + regulator-enable-ramp-delay = <400>;
> + regulator-min-microvolt = <550000>;
> + regulator-max-microvolt = <950000>;
> + regulator-ramp-delay = <12500>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vdd_cpu_lit_s0: dcdc-reg2 {
> + regulator-name = "vdd_cpu_lit_s0";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <550000>;
> + regulator-max-microvolt = <950000>;
> + regulator-ramp-delay = <12500>;
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vccio_sd_s0: pldo-reg5 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vccio_sd_s0";
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vdd2_ddr_s3: dcdc-reg6 {
> + regulator-name = "vdd2_ddr_s3";
> + regulator-always-on;
> + regulator-boot-on;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + };
> + };
> +
> + vcc_2v0_pldo_s3: dcdc-reg7 {
> + regulator-name = "vdd_2v0_pldo_s3";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <2000000>;
> + regulator-max-microvolt = <2000000>;
> + regulator-ramp-delay = <12500>;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <2000000>;
> + };
> + };
> +
> + vcc_3v3_s3: dcdc-reg8 {
> + regulator-name = "vcc_3v3_s3";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <3300000>;
> + };
> + };
> + };
> + };
> +};
> +
> +&u2phy0 {
> + status = "okay";
> +};
> +
> +&u2phy0_otg {
> + status = "okay";
> +};
> +
> +&u2phy2 {
> + status = "okay";
> +};
> +
> +&u2phy2_host {
> + status = "okay";
> +};
> +
> +&u2phy3 {
> + status = "okay";
> +};
> +
> +&u2phy3_host {
> + status = "okay";
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart2m0_xfer>;
> + status = "okay";
> +};
> +
> +&usb_host0_ehci {
> + status = "okay";
> +};
> +
> +&usb_host0_ohci {
> + status = "okay";
> +};
> +
> +&usb_host0_xhci {
> + dr_mode = "otg";
> + usb-role-switch;
> + status = "okay";
> +
> + port {
> + usb_host0_xhci_role_switch: endpoint {
> + remote-endpoint = <&usbc0_role_switch>;
> + };
> + };
> +};
> +
> +&usb_host1_ehci {
> + status = "okay";
> +};
> +
> +&usb_host1_ohci {
> + status = "okay";
> +};
> +
Is the combphy2_psu used for a USB 3.0 port? If so, you'll need to
enable usb_host2_xhci.
> +&usbdp_phy0 {
> + mode-switch;
> + orientation-switch;
> + sbu1-dc-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
> + sbu2-dc-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +
> + port {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + usbdp_phy0_orientation_switch: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&usbc0_orientation_switch>;
> + };
> +
> + usbdp_phy0_dp_altmode_mux: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&usbc0_dp_altmode_mux>;
> + };
> + };
> +};
> +
> +&vop {
> + status = "okay";
> +};
> +
> +&vop_mmu {
> + status = "okay";
> +};
> +
> +&vp0 {
> + vp0_out_hdmi0: endpoint@...KCHIP_VOP2_EP_HDMI0 {
> + reg = <ROCKCHIP_VOP2_EP_HDMI0>;
> + remote-endpoint = <&hdmi0_in_vp0>;
> + };
> +};
Jimmy
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