linux-kernel - Re: [PATCH 8/9] ARM: dts: microchip: sama7d65: Add CAN bus support

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Message-ID: <201c7188-eaf7-4492-84a6-66d839062d8d@tuxon.dev>
Date: Sat, 7 Jun 2025 14:43:45 +0300
From: Claudiu Beznea <claudiu.beznea@...on.dev>
To: Ryan.Wanner@...rochip.com, herbert@...dor.apana.org.au,
 davem@...emloft.net, robh@...nel.org, krzk+dt@...nel.org,
 conor+dt@...nel.org, nicolas.ferre@...rochip.com,
 alexandre.belloni@...tlin.com, olivia@...enic.com
Cc: linux-crypto@...r.kernel.org, devicetree@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 8/9] ARM: dts: microchip: sama7d65: Add CAN bus support



On 12.05.2025 22:27, Ryan.Wanner@...rochip.com wrote:
> From: Ryan Wanner <Ryan.Wanner@...rochip.com>
> 
> Add support for CAN bus to the SAMA7D65 SoC.
> 
> Signed-off-by: Ryan Wanner <Ryan.Wanner@...rochip.com>

Reviewed-by: Claudiu Beznea <claudiu.beznea@...on.dev>

> ---
>  arch/arm/boot/dts/microchip/sama7d65.dtsi | 80 +++++++++++++++++++++++
>  1 file changed, 80 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> index 796909fa2368..a62d2ef9fcab 100644
> --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
> +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> @@ -163,6 +163,86 @@ chipid@...20000 {
>  			reg = <0xe0020000 0x8>;
>  		};
>  
> +		can0: can@...28000 {
> +			compatible = "bosch,m_can";
> +			reg = <0xe0828000 0x200>, <0x100000 0x7800>;
> +			reg-names = "m_can", "message_ram";
> +			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "int0", "int1";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>;
> +			clock-names = "hclk", "cclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 58>;
> +			assigned-clock-rates = <40000000>;
> +			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
> +			status = "disabled";
> +		};
> +
> +		can1: can@...2c000 {
> +			compatible = "bosch,m_can";
> +			reg = <0xe082c000 0x200>, <0x100000 0xbc00>;
> +			reg-names = "m_can", "message_ram";
> +			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "int0", "int1";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>;
> +			clock-names = "hclk", "cclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 59>;
> +			assigned-clock-rates = <40000000>;
> +			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
> +			status = "disabled";
> +		};
> +
> +		can2: can@...30000 {
> +			compatible = "bosch,m_can";
> +			reg = <0xe0830000 0x200>, <0x100000 0x10000>;
> +			reg-names = "m_can", "message_ram";
> +			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "int0", "int1";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 60>, <&pmc PMC_TYPE_GCK 60>;
> +			clock-names = "hclk", "cclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 60>;
> +			assigned-clock-rates = <40000000>;
> +			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>;
> +			status = "disabled";
> +		};
> +
> +		can3: can@...34000 {
> +			compatible = "bosch,m_can";
> +			reg = <0xe0834000 0x200>, <0x110000 0x4400>;
> +			reg-names = "m_can", "message_ram";
> +			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "int0", "int1";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>;
> +			clock-names = "hclk", "cclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 61>;
> +			assigned-clock-rates = <40000000>;
> +			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
> +			status = "disabled";
> +		};
> +
> +		can4: can@...38000 {
> +			compatible = "bosch,m_can";
> +			reg = <0xe0838000 0x200>, <0x110000 0x8800>;
> +			reg-names = "m_can", "message_ram";
> +			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "int0", "int1";
> +			clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>;
> +			clock-names = "hclk", "cclk";
> +			assigned-clocks = <&pmc PMC_TYPE_GCK 62>;
> +			assigned-clock-rates = <40000000>;
> +			assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> +			bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>;
> +			status = "disabled";
> +		};
> +
>  		dma2: dma-controller@...00000 {
>  			compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma";
>  			reg = <0xe1200000 0x1000>;