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Message-ID: <20250608232836.784737-2-inochiama@gmail.com>
Date: Mon, 9 Jun 2025 07:28:25 +0800
From: Inochi Amaoto <inochiama@...il.com>
To: Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Alexandre Ghiti <alex@...ti.fr>,
Chen Wang <unicorn_wang@...look.com>,
Inochi Amaoto <inochiama@...il.com>,
Richard Cochran <richardcochran@...il.com>,
Longbin Li <looong.bin@...il.com>
Cc: Han Gao <rabenda.cn@...il.com>,
devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org,
sophgo@...ts.linux.dev,
linux-kernel@...r.kernel.org,
netdev@...r.kernel.org,
Yixun Lan <dlan@...too.org>
Subject: [PATCH 01/11] riscv: dts: sophgo: sg2044: Add system controller device
The TOP system controller device is necessary for the SG2044 clock
controller. Add it to the SoC device tree.
Signed-off-by: Inochi Amaoto <inochiama@...il.com>
---
arch/riscv/boot/dts/sophgo/sg2044.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
index d67e45f77d6e..a0c13d8d26af 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
@@ -76,6 +76,13 @@ uart3: serial@...0003000 {
status = "disabled";
};
+ syscon: syscon@...0000000 {
+ compatible = "sophgo,sg2044-top-syscon", "syscon";
+ reg = <0x70 0x50000000 0x0 0x1000>;
+ #clock-cells = <1>;
+ clocks = <&osc>;
+ };
+
rst: reset-controller@...0003000 {
compatible = "sophgo,sg2044-reset",
"sophgo,sg2042-reset";
--
2.49.0
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