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Message-ID: <20250608232836.784737-7-inochiama@gmail.com>
Date: Mon, 9 Jun 2025 07:28:30 +0800
From: Inochi Amaoto <inochiama@...il.com>
To: Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Alexandre Ghiti <alex@...ti.fr>,
Chen Wang <unicorn_wang@...look.com>,
Inochi Amaoto <inochiama@...il.com>,
Richard Cochran <richardcochran@...il.com>,
Longbin Li <looong.bin@...il.com>
Cc: Han Gao <rabenda.cn@...il.com>,
devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org,
netdev@...r.kernel.org,
Yixun Lan <dlan@...too.org>
Subject: [PATCH 06/11] riscv: dts: sophgo: sg2044: Add MMC controller device
Add emmc controller and sd controller DT node for SG2044.
Signed-off-by: Inochi Amaoto <inochiama@...il.com>
---
.../boot/dts/sophgo/sg2044-sophgo-srd3-10.dts | 17 +++++++++++++
arch/riscv/boot/dts/sophgo/sg2044.dtsi | 24 +++++++++++++++++++
2 files changed, 41 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
index 54cdf4239d5f..d077923097e8 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2044-sophgo-srd3-10.dts
@@ -27,6 +27,23 @@ &osc {
clock-frequency = <25000000>;
};
+&emmc {
+ bus-width = <4>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ wp-inverted;
+ status = "okay";
+};
+
+&sd {
+ bus-width = <4>;
+ no-sdio;
+ no-mmc;
+ wp-inverted;
+ status = "okay";
+};
+
&uart1 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
index a4d2f8a13cc3..6067901cde1e 100644
--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
@@ -111,6 +111,30 @@ uart3: serial@...0003000 {
status = "disabled";
};
+ emmc: mmc@...000a000 {
+ compatible = "sophgo,sg2044-dwcmshc", "sophgo,sg2042-dwcmshc";
+ reg = <0x70 0x3000a000 0x0 0x1000>;
+ clocks = <&clk CLK_GATE_EMMC>,
+ <&clk CLK_GATE_AXI_EMMC>,
+ <&clk CLK_GATE_EMMC_100K>;
+ clock-names = "core", "bus", "timer";
+ interrupt-parent = <&intc>;
+ interrupts = <298 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ sd: mmc@...000b000 {
+ compatible = "sophgo,sg2044-dwcmshc", "sophgo,sg2042-dwcmshc";
+ reg = <0x70 0x3000b000 0x0 0x1000>;
+ clocks = <&clk CLK_GATE_SD>,
+ <&clk CLK_GATE_AXI_SD>,
+ <&clk CLK_GATE_SD_100K>;
+ clock-names = "core", "bus", "timer";
+ interrupt-parent = <&intc>;
+ interrupts = <300 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
i2c0: i2c@...0005000 {
compatible = "sophgo,sg2044-i2c", "snps,designware-i2c";
reg = <0x70 0x40005000 0x0 0x1000>;
--
2.49.0
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