linux-kernel - [PATCH v11 03/13] x86/msr-index: define AMD heterogeneous CPU related MSR

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Message-ID: <20250609200518.3616080-4-superm1@kernel.org>
Date: Mon,  9 Jun 2025 15:05:08 -0500
From: Mario Limonciello <superm1@...nel.org>
To: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
Cc: Mario Limonciello <mario.limonciello@....com>,
	Perry Yuan <perry.yuan@....com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...hat.com>,
	Borislav Petkov <bp@...en8.de>,
	Dave Hansen <dave.hansen@...ux.intel.com>,
	x86@...nel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)),
	"H . Peter Anvin" <hpa@...or.com>,
	Jonathan Corbet <corbet@....net>,
	Huang Rui <ray.huang@....com>,
	"Gautham R . Shenoy" <gautham.shenoy@....com>,
	"Rafael J . Wysocki" <rafael@...nel.org>,
	Viresh Kumar <viresh.kumar@...aro.org>,
	platform-driver-x86@...r.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER),
	linux-kernel@...r.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)),
	linux-doc@...r.kernel.org (open list:DOCUMENTATION),
	linux-pm@...r.kernel.org (open list:AMD PSTATE DRIVER)
Subject: [PATCH v11 03/13] x86/msr-index: define AMD heterogeneous CPU related MSR

From: Perry Yuan <perry.yuan@....com>

Introduces new MSR registers for AMD hardware feedback support.
These registers enable the system to provide workload classification
and configuration capabilities.

Reviewed-by: Gautham R. Shenoy <gautham.shenoy@....com>
Signed-off-by: Perry Yuan <perry.yuan@....com>
Signed-off-by: Mario Limonciello <mario.limonciello@....com>
---
v11:
 * Prefix new MSRs with MSR_AMD
---
 arch/x86/include/asm/msr-index.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index b7dded3c81132..4dbf6dbf4c1da 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -732,6 +732,11 @@
 #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL		0xc0000301
 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR	0xc0000302
 
+/* AMD Hardware Feedback Support MSRs */
+#define MSR_AMD_WORKLOAD_CLASS_CONFIG		0xc0000500
+#define MSR_AMD_WORKLOAD_CLASS_ID		0xc0000501
+#define MSR_AMD_WORKLOAD_HRST			0xc0000502
+
 /* AMD Last Branch Record MSRs */
 #define MSR_AMD64_LBR_SELECT			0xc000010e
 
-- 
2.43.0