Message-ID: <20250609203656.333138-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Mon,  9 Jun 2025 21:36:48 +0100
From: Prabhakar <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
	Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Magnus Damm <magnus.damm@...il.com>
Cc: linux-renesas-soc@...r.kernel.org,
	linux-clk@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Prabhakar <prabhakar.csengg@...il.com>,
	Biju Das <biju.das.jz@...renesas.com>,
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
	Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH 0/8] Add support for Renesas RZ/N2H (R9A09G087) SoC and RZ/N2H EVK

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>

Hi All,

This patch series adds support for the Renesas RZ/N2H (R9A09G087) SoC and
the RZ/N2H EVK (R9A09G087M44-RZN2H-EVK) evaluation board. The RZ/N2H SoC
is very much similar to the RZ/T2H (R9A09G077) SoC. 

RZ/N2H is a high-performance MPU that delivers advanced application
processing and real-time operation for industrial applications. It
features a quad-core Arm Cortex-A55 and dual-core Arm Cortex-R52
configuration, with security features, and is designed for real-time
control and high-speed communication.

RZ/N2H SoC supports below features:
- Quad-core Arm Cortex-A55 and dual-core Arm Cortex-R52 configuration
- Security functions (optional)
- Encoder interfaces
  * 16 channels
  * EnDat 2.2, BiSS-C, A-format, and HIPERFACE DSL-compliant interfaces
  * Frequency-divided output from an encoder
- Various communications interfaces
  * Ethernet
    - EtherCAT slave Controller: 3 ports
    - Ethernet switch: 3 ports
    - Ethernet MAC: 1 port x 3 units
  *  USB 2.0 high-speed host/functions: 1 channel
  * CAN/CANFD (compliant with ISO11898-1): 2 channels
  * SCI with 16-byte transmission and reception FIFOs: 6 channels +
    12 channels (for encoder)
  * I2C bus interface: 3 channel for transfer at up to 400 kbps
  * SPI: 4 channels
  * xSPI: 2 channels
  * PCI Express Gen3: 2 lane x 1 port or 1 lane x 2 ports
  * SD card host interface: 2 channels
- Serial host interface
- 12 bits x 3 unit (4 channels for unit 0, 1, 15 channels for unit 2
- LCD Controller
- General-purpose I/O ports
- Trigonometric function unit
- 16-bit x 8 + 32-bit MTU3 (9 channels), 32-bit GPT (56 channels)
- 6-bit CMT (6 channels), 32-bit CMTW (2 channels)

For more information, please refer to the product page:

https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rzn2h-advanced-mpu-delivers-high-performance-application-processing-and-real-time-operation-industrial?srsltid=AfmBOoro9kUrZ77ugeURFIlE5ToiFazSyzIsbjBDdGs83NHZfhlkFHlJ

Note, this patch series applies on top of the patch series
- "Add initial support for Renesas RZ/T2H SoC" [1].
- "dt-bindings: serial: renesas,rsci: Document RZ/N2H support" [2].

[1] https://lore.kernel.org/all/20250523142417.2840797-1-thierry.bultel.yh@bp.renesas.com/
[2] https://lore.kernel.org/all/20250609192344.293317-1-prabhakar.mahadev-lad.rj@bp.renesas.com/

Cheers,
Prabhakar

Lad Prabhakar (4):
  soc: renesas: Add config option for RZ/N2H (R9A09G087) SoC
  dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support
  clk: renesas: Add MSSR support to RZ/N2H SoC
  arm64: dts: renesas: Add initial SoC DTSI for RZ/N2H SoC

Paul Barker (4):
  dt-bindings: soc: Add Renesas RZ/N2H (R9A09G087) SoC
  arm64: dts: renesas: Refactor RZ/T2H EVK device tree
  arm64: dts: renesas: Add DTSI for R9A09G087M44 variant of RZ/N2H SoC
  arm64: dts: renesas: Add initial support for RZ/N2H EVK

 .../bindings/clock/renesas,cpg-mssr.yaml      |   5 +-
 .../bindings/soc/renesas/renesas.yaml         |  10 ++
 arch/arm64/boot/dts/renesas/Makefile          |   1 +
 .../dts/renesas/r9a09g077m44-rzt2h-evk.dts    |  17 +--
 arch/arm64/boot/dts/renesas/r9a09g087.dtsi    | 135 ++++++++++++++++++
 .../dts/renesas/r9a09g087m44-rzn2h-evk.dts    |  16 +++
 arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi |  13 ++
 .../boot/dts/renesas/rzt2h-evk-common.dtsi    |  24 ++++
 drivers/clk/renesas/Kconfig                   |   5 +
 drivers/clk/renesas/Makefile                  |   1 +
 drivers/clk/renesas/r9a09g077-cpg.c           |   1 +
 drivers/clk/renesas/renesas-cpg-mssr.c        |   6 +
 drivers/soc/renesas/Kconfig                   |   6 +
 .../clock/renesas,r9a09g087-cpg-mssr.h        |  28 ++++
 14 files changed, 251 insertions(+), 17 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g087.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g087m44.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/rzt2h-evk-common.dtsi
 create mode 100644 include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h

-- 
2.49.0

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