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Message-ID: <CAK9=C2VhmU1a9TN4+oLMNRfweHY8jw=W71k+HpqnUxxve6hNfQ@mail.gmail.com>
Date: Mon, 9 Jun 2025 11:28:06 +0530
From: Anup Patel <apatel@...tanamicro.com>
To: Atish Patra <atish.patra@...ux.dev>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, 
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Jassi Brar <jassisinghbrar@...il.com>, Thomas Gleixner <tglx@...utronix.de>, 
	"Rafael J . Wysocki" <rafael@...nel.org>, Mika Westerberg <mika.westerberg@...ux.intel.com>, 
	Andy Shevchenko <andriy.shevchenko@...ux.intel.com>, 
	Linus Walleij <linus.walleij@...aro.org>, Bartosz Golaszewski <brgl@...ev.pl>, 
	Uwe Kleine-König <ukleinek@...nel.org>, 
	Palmer Dabbelt <palmer@...belt.com>, Paul Walmsley <paul.walmsley@...ive.com>, 
	Len Brown <lenb@...nel.org>, Sunil V L <sunilvl@...tanamicro.com>, 
	Rahul Pathak <rpathak@...tanamicro.com>, Leyfoon Tan <leyfoon.tan@...rfivetech.com>, 
	Andrew Jones <ajones@...tanamicro.com>, Samuel Holland <samuel.holland@...ive.com>, 
	Anup Patel <anup@...infault.org>, linux-clk@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 01/23] riscv: Add new error codes defined by SBI v3.0

On Sat, Jun 7, 2025 at 5:21 AM Atish Patra <atish.patra@...ux.dev> wrote:
>
>
> On 5/25/25 1:46 AM, Anup Patel wrote:
> > The SBI v3.0 defines new error codes so add these new error codes
> > to the asm/sbi.h for use by newer SBI extensions.
>
> This patch can be dropped as it is part of the FWFT series with minor
> modifications in error mappings.
>
> https://lore.kernel.org/linux-riscv/20250523101932.1594077-4-cleger@rivosinc.com/

Yes, I am aware of Clement's patch. I was temporarily carrying
this patch over here.

Regards,
Anup

>
>
> > Signed-off-by: Anup Patel <apatel@...tanamicro.com>
> > ---
> >   arch/riscv/include/asm/sbi.h | 12 ++++++++++++
> >   1 file changed, 12 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> > index 3d250824178b..4dd6aafb8468 100644
> > --- a/arch/riscv/include/asm/sbi.h
> > +++ b/arch/riscv/include/asm/sbi.h
> > @@ -419,6 +419,11 @@ enum sbi_ext_nacl_feature {
> >   #define SBI_ERR_ALREADY_STARTED -7
> >   #define SBI_ERR_ALREADY_STOPPED -8
> >   #define SBI_ERR_NO_SHMEM    -9
> > +#define SBI_ERR_INVALID_STATE        -10
> > +#define SBI_ERR_BAD_RANGE    -11
> > +#define SBI_ERR_TIMEOUT              -12
> > +#define SBI_ERR_IO           -13
> > +#define SBI_ERR_DENIED_LOCKED        -14
> >
> >   extern unsigned long sbi_spec_version;
> >   struct sbiret {
> > @@ -503,11 +508,18 @@ static inline int sbi_err_map_linux_errno(int err)
> >       case SBI_SUCCESS:
> >               return 0;
> >       case SBI_ERR_DENIED:
> > +     case SBI_ERR_DENIED_LOCKED:
> >               return -EPERM;
> >       case SBI_ERR_INVALID_PARAM:
> > +     case SBI_ERR_INVALID_STATE:
> > +     case SBI_ERR_BAD_RANGE:
> >               return -EINVAL;
> >       case SBI_ERR_INVALID_ADDRESS:
> >               return -EFAULT;
> > +     case SBI_ERR_TIMEOUT:
> > +             return -ETIMEDOUT;
> > +     case SBI_ERR_IO:
> > +             return -EIO;
> >       case SBI_ERR_NOT_SUPPORTED:
> >       case SBI_ERR_FAILURE:
> >       default:

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