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Message-ID: <20250609-msm-dp-mst-v2-11-a54d8902a23d@quicinc.com>
Date: Mon, 9 Jun 2025 20:21:30 +0800
From: Yongxing Mou <quic_yongmou@...cinc.com>
To: Rob Clark <robin.clark@....qualcomm.com>,
Dmitry Baryshkov
<lumag@...nel.org>,
Abhinav Kumar <abhinav.kumar@...ux.dev>,
Jessica Zhang
<jessica.zhang@....qualcomm.com>,
Sean Paul <sean@...rly.run>,
Marijn Suijten
<marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, "Simona
Vetter" <simona@...ll.ch>
CC: <linux-arm-msm@...r.kernel.org>, <dri-devel@...ts.freedesktop.org>,
<freedreno@...ts.freedesktop.org>, <linux-kernel@...r.kernel.org>,
"Yongxing
Mou" <quic_yongmou@...cinc.com>,
Abhinav Kumar <quic_abhinavk@...cinc.com>
Subject: [PATCH v2 11/38] drm/msm/dp: introduce stream_id for each DP panel
From: Abhinav Kumar <quic_abhinavk@...cinc.com>
With MST, each DP controller can handle multiple streams.
There shall be one dp_panel for each stream but the dp_display
object shall be shared among them. To represent this abstraction,
create a stream_id for each DP panel which shall be set by the
MST stream. For SST, default this to stream 0.
Use the stream ID to control the pixel clock of that respective
stream by extending the clock handles and state tracking of the
DP pixel clock to an array of max supported streams. The maximum
streams currently is 4.
Signed-off-by: Abhinav Kumar <quic_abhinavk@...cinc.com>
Signed-off-by: Yongxing Mou <quic_yongmou@...cinc.com>
---
drivers/gpu/drm/msm/dp/dp_catalog.h | 9 ++++++
drivers/gpu/drm/msm/dp/dp_ctrl.c | 55 ++++++++++++++++++++++---------------
drivers/gpu/drm/msm/dp/dp_ctrl.h | 4 +--
drivers/gpu/drm/msm/dp/dp_display.c | 27 ++++++++++++++++--
drivers/gpu/drm/msm/dp/dp_display.h | 2 ++
drivers/gpu/drm/msm/dp/dp_panel.h | 2 ++
6 files changed, 72 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h
index 6678b0ac9a67881244884d59487fa288d33d1be7..f9e7506afcf4f4d932665462ca316f6c66c662a6 100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.h
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.h
@@ -31,6 +31,15 @@
#define DP_HW_VERSION_1_0 0x10000000
#define DP_HW_VERSION_1_2 0x10020000
+/* stream id */
+enum msm_dp_stream_id {
+ DP_STREAM_0,
+ DP_STREAM_1,
+ DP_STREAM_2,
+ DP_STREAM_3,
+ DP_STREAM_MAX,
+};
+
struct msm_dp_catalog {
bool wide_bus_en;
};
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index c990a7a835fc9645c2dd7e1ec8604e991baf754a..7db23968c4227557d3cea9bfbf5aa3c3e17a87d8 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -87,7 +87,7 @@ struct msm_dp_ctrl_private {
unsigned int num_link_clks;
struct clk_bulk_data *link_clks;
- struct clk *pixel_clk;
+ struct clk *pixel_clk[DP_STREAM_MAX];
union phy_configure_opts phy_opts;
@@ -97,7 +97,7 @@ struct msm_dp_ctrl_private {
bool core_clks_on;
bool link_clks_on;
- bool pixel_clks_on;
+ bool pixel_clks_on[DP_STREAM_MAX];
};
static int msm_dp_aux_link_configure(struct drm_dp_aux *aux,
@@ -1737,39 +1737,40 @@ static bool msm_dp_ctrl_send_phy_test_pattern(struct msm_dp_ctrl_private *ctrl)
return success;
}
-static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsigned long pixel_rate)
+static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsigned long pixel_rate,
+ enum msm_dp_stream_id stream_id)
{
int ret;
- ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000);
+ ret = clk_set_rate(ctrl->pixel_clk[stream_id], pixel_rate * 1000);
if (ret) {
DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret);
return ret;
}
- if (ctrl->pixel_clks_on) {
+ if (ctrl->pixel_clks_on[stream_id]) {
drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n");
} else {
- ret = clk_prepare_enable(ctrl->pixel_clk);
+ ret = clk_prepare_enable(ctrl->pixel_clk[stream_id]);
if (ret) {
DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret);
return ret;
}
- ctrl->pixel_clks_on = true;
+ ctrl->pixel_clks_on[stream_id] = true;
}
return ret;
}
-void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl)
+void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl, enum msm_dp_stream_id stream_id)
{
struct msm_dp_ctrl_private *ctrl;
ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
- if (ctrl->pixel_clks_on) {
- clk_disable_unprepare(ctrl->pixel_clk);
- ctrl->pixel_clks_on = false;
+ if (ctrl->pixel_clks_on[stream_id]) {
+ clk_disable_unprepare(ctrl->pixel_clk[stream_id]);
+ ctrl->pixel_clks_on[stream_id] = false;
}
}
@@ -1790,7 +1791,7 @@ static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private *ctrl
* running. Add the global reset just before disabling the
* link clocks and core clocks.
*/
- msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl);
+ msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl, msm_dp_panel->stream_id);
msm_dp_ctrl_off_link(&ctrl->msm_dp_ctrl);
ret = msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl);
@@ -1800,7 +1801,7 @@ static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private *ctrl
}
pixel_rate = msm_dp_panel->msm_dp_mode.drm_mode.clock;
- ret = msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate);
+ ret = msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate, msm_dp_panel->stream_id);
msm_dp_ctrl_send_phy_test_pattern(ctrl);
@@ -2020,8 +2021,8 @@ int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool force_li
ctrl->link->link_params.num_lanes);
drm_dbg_dp(ctrl->drm_dev,
- "core_clk_on=%d link_clk_on=%d pixel_clks_on=%d\n",
- ctrl->core_clks_on, ctrl->link_clks_on, ctrl->pixel_clks_on);
+ "core_clk_on=%d link_clk_on=%d\n",
+ ctrl->core_clks_on, ctrl->link_clks_on);
if (!ctrl->link_clks_on) { /* link clk is off */
ret = msm_dp_ctrl_enable_mainlink_clocks(ctrl);
@@ -2060,7 +2061,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *
drm_dbg_dp(ctrl->drm_dev, "pixel_rate=%lu\n", pixel_rate);
- ret = msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate);
+ ret = msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate, msm_dp_panel->stream_id);
if (ret) {
DRM_ERROR("failed to enable pixel clk\n");
return ret;
@@ -2205,10 +2206,11 @@ static const char *ctrl_clks[] = {
"ctrl_link_iface",
};
-static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *msm_dp_ctrl)
+static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *msm_dp_ctrl, int max_stream)
{
struct msm_dp_ctrl_private *ctrl;
struct device *dev;
+ char stream_id_str[15];
int i, rc;
ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
@@ -2238,17 +2240,26 @@ static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *msm_dp_ctrl)
if (rc)
return rc;
- ctrl->pixel_clk = devm_clk_get(dev, "stream_pixel");
- if (IS_ERR(ctrl->pixel_clk))
- return PTR_ERR(ctrl->pixel_clk);
+ ctrl->pixel_clk[DP_STREAM_0] = devm_clk_get(dev, "stream_pixel");
+ if (IS_ERR(ctrl->pixel_clk[DP_STREAM_0]))
+ return PTR_ERR(ctrl->pixel_clk[DP_STREAM_0]);
+ for (i = DP_STREAM_1; i < max_stream; i++) {
+ sprintf(stream_id_str, "stream_%d_pixel", i);
+ ctrl->pixel_clk[i] = devm_clk_get(dev, stream_id_str);
+
+ if (IS_ERR(ctrl->pixel_clk[i])) {
+ DRM_DEBUG_DP("failed to get stream %d pixel clock", i);
+ break;
+ }
+ }
return 0;
}
struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link,
struct msm_dp_panel *panel, struct drm_dp_aux *aux,
struct msm_dp_catalog *catalog,
- struct phy *phy)
+ struct phy *phy, int max_stream)
{
struct msm_dp_ctrl_private *ctrl;
int ret;
@@ -2289,7 +2300,7 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link
ctrl->dev = dev;
ctrl->phy = phy;
- ret = msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl);
+ ret = msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl, max_stream);
if (ret) {
dev_err(dev, "failed to init clocks\n");
return ERR_PTR(ret);
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h
index f14778c5dfaad7e9cb697697d873977d109e6cfc..e20ba90dbd879ae3d6b1f5eb5922f969bc12d079 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.h
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h
@@ -21,14 +21,14 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl);
int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel *msm_dp_panel);
int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *dp_ctrl, bool force_link_train);
void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl);
-void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl);
+void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl, enum msm_dp_stream_id stream_id);
void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl);
irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl);
void msm_dp_ctrl_handle_sink_request(struct msm_dp_ctrl *msm_dp_ctrl);
struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link,
struct msm_dp_panel *panel, struct drm_dp_aux *aux,
struct msm_dp_catalog *catalog,
- struct phy *phy);
+ struct phy *phy, int max_stream);
void msm_dp_ctrl_reset_irq_ctrl(struct msm_dp_ctrl *msm_dp_ctrl, bool enable);
void msm_dp_ctrl_phy_init(struct msm_dp_ctrl *msm_dp_ctrl);
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
index 4e0213cae4aafb468681db27b3c3fef28d44b2c0..a13e4007858701787562eded7b6fc8f7171e167b 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -784,7 +784,7 @@ static int msm_dp_init_sub_modules(struct msm_dp_display_private *dp)
dp->ctrl = msm_dp_ctrl_get(dev, dp->link, dp->panel, dp->aux,
dp->catalog,
- phy);
+ phy, dp->max_stream);
if (IS_ERR(dp->ctrl)) {
rc = PTR_ERR(dp->ctrl);
DRM_ERROR("failed to initialize ctrl, rc = %d\n", rc);
@@ -934,12 +934,12 @@ static int msm_dp_display_disable(struct msm_dp_display_private *dp)
/* dongle is still connected but sinks are disconnected */
if (dp->link->sink_count == 0) {
msm_dp_ctrl_psm_config(dp->ctrl);
- msm_dp_ctrl_off_pixel_clk(dp->ctrl);
+ msm_dp_ctrl_off_pixel_clk(dp->ctrl, dp->panel->stream_id);
msm_dp_ctrl_off_link(dp->ctrl);
/* re-init the PHY so that we can listen to Dongle disconnect */
msm_dp_ctrl_reinit_phy(dp->ctrl);
} else {
- msm_dp_ctrl_off_pixel_clk(dp->ctrl);
+ msm_dp_ctrl_off_pixel_clk(dp->ctrl, dp->panel->stream_id);
msm_dp_ctrl_off_link(dp->ctrl);
msm_dp_display_host_phy_exit(dp);
}
@@ -950,6 +950,25 @@ static int msm_dp_display_disable(struct msm_dp_display_private *dp)
return 0;
}
+int msm_dp_display_set_stream_id(struct msm_dp *dp,
+ struct msm_dp_panel *panel, enum msm_dp_stream_id stream_id)
+{
+ int rc = 0;
+ struct msm_dp_display_private *msm_dp_display;
+
+ msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display);
+
+ if (!msm_dp_display) {
+ DRM_ERROR("invalid input\n");
+ return -EINVAL;
+ }
+
+ if (panel)
+ panel->stream_id = stream_id;
+
+ return rc;
+}
+
/**
* msm_dp_bridge_mode_valid - callback to determine if specified mode is valid
* @dp: Pointer to dp display structure
@@ -1574,6 +1593,8 @@ void msm_dp_display_atomic_enable(struct msm_dp *dp)
mutex_lock(&msm_dp_display->event_mutex);
+ msm_dp_display_set_stream_id(dp, msm_dp_display->panel, 0);
+
if (dp->prepared) {
rc = msm_dp_display_enable(msm_dp_display);
if (rc)
diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h
index 4e3540f2eb21afb14583b0d521dd9817fefd2f70..09b30596fd3366af55ae246e3a83ee9e88995382 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.h
+++ b/drivers/gpu/drm/msm/dp/dp_display.h
@@ -45,5 +45,7 @@ void msm_dp_display_mode_set(struct msm_dp *dp,
enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp,
const struct drm_display_info *info,
const struct drm_display_mode *mode);
+int msm_dp_display_set_stream_id(struct msm_dp *dp,
+ struct msm_dp_panel *panel, enum msm_dp_stream_id stream_id);
#endif /* _DP_DISPLAY_H_ */
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h
index 7f139478e1012d5b8f1f745f0de5fc3943745428..170f819644b473b454f88cd4e8762959f4513613 100644
--- a/drivers/gpu/drm/msm/dp/dp_panel.h
+++ b/drivers/gpu/drm/msm/dp/dp_panel.h
@@ -38,6 +38,8 @@ struct msm_dp_panel {
bool video_test;
bool vsc_sdp_supported;
+ enum msm_dp_stream_id stream_id;
+
u32 max_dp_lanes;
u32 max_dp_link_rate;
--
2.34.1
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