linux-kernel - [PATCH v1 0/7] Risc-V ACLINT IPI controller

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Message-ID: <20250609134749.1453835-1-vladimir.kondratiev@mobileye.com>
Date: Mon,  9 Jun 2025 16:47:42 +0300
From: Vladimir Kondratiev <vladimir.kondratiev@...ileye.com>
To: Thomas Gleixner <tglx@...utronix.de>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>,
	Alexandre Ghiti <alex@...ti.fr>,
	Anup Patel <anup@...infault.org>,
	Chen Wang <unicorn_wang@...look.com>,
	Inochi Amaoto <inochiama@...il.com>,
	Sunil V L <sunilvl@...tanamicro.com>,
	"Rafael J . Wysocki" <rafael.j.wysocki@...el.com>,
	Ryo Takakura <takakura@...inux.co.jp>
Cc: linux-kernel@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-riscv@...ts.infradead.org,
	sophgo@...ts.linux.dev,
	Vladimir Kondratiev <vladimir.kondratiev@...ileye.com>
Subject: [PATCH v1 0/7] Risc-V ACLINT IPI controller

Risc-V specification for the ACLINT IPI controller
describes an "SSWI" device that allows to send IPI by
writing register from the S-mode (Linux kernel),
as opposed to the "MSWI" device that does the same from
the M-mode. Sending IPI through the M-mode requires
extra SBI call, SSWI is much faster. Support for the
SSWI exists for the Thead board, it is almost as by
specification save for reading one custom CSR.

Soon to be released Mobileye SoC based on the MIPS
P8700 Risc-v CPU has pristine ACLINT SSWI.

To support P8700, refactor Thead implementation -
provide generic one while keeping Thead-specific variant.

In addition, support Risc-v "hart index" - it is
required for the MIPS P8700 chip to be released soon

Patches 1 and 2 refactor "hart index" support, replacing
APLIC specific implementation with generic helper

Patch 3 documents generic "riscv,aclint-sswi" and optional
property "riscv,hart-indexes", same as for ACLINT.

Patch 4 promotes Thead-specific SSWI to generic one

Patch 5 adds "riscv,hart-indexes" support

Patches 6 and 7 do some minor improvements for the SSWI

Vladimir Kondratiev (7):
  riscv: helper to parse hart index
  irqchip: riscv aplic: use riscv_get_hart_index()
  dt-bindings: interrupt-controller: add generic Risc-v aclint-sswi
  irqchip: introduce generic Risc-V aclint-sswi
  irqchip: aslint-sswi: resolve hart index
  irqchip: aclint-sswi: reduce data scope
  irqchip: aclint-sswi: remove extra includes

 .../riscv,aclint-sswi.yaml                    |  89 ++++++++++++++
 .../thead,c900-aclint-sswi.yaml               |  58 ---------
 arch/riscv/include/asm/irq.h                  |   2 +
 arch/riscv/kernel/irq.c                       |  34 ++++++
 drivers/irqchip/Kconfig                       |  12 ++
 drivers/irqchip/Makefile                      |   2 +-
 ...d-c900-aclint-sswi.c => irq-aclint-sswi.c} | 114 ++++++++++++------
 drivers/irqchip/irq-riscv-aplic-direct.c      |  16 +--
 8 files changed, 214 insertions(+), 113 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aclint-sswi.yaml
 delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml
 rename drivers/irqchip/{irq-thead-c900-aclint-sswi.c => irq-aclint-sswi.c} (63%)


base-commit: 19272b37aa4f83ca52bdf9c16d5d81bdd1354494
-- 
2.43.0