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Message-ID: <902db298b21cf78a2c27ed0cdc002e7f2861c428.camel@gmail.com>
Date: Mon, 09 Jun 2025 18:39:43 +0200
From: Alexander Sverdlin <alexander.sverdlin@...il.com>
To: Inochi Amaoto <inochiama@...il.com>, Philipp Zabel
<p.zabel@...gutronix.de>, Rob Herring <robh@...nel.org>, Krzysztof
Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Chen
Wang <unicorn_wang@...look.com>, Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
Alexandre Ghiti <alex@...ti.fr>, Yixun Lan <dlan@...too.org>, Thomas
Bonnefille <thomas.bonnefille@...tlin.com>, Ze Huang <huangze@...t.edu.cn>
Cc: Junhui Liu <junhui.liu@...moral.tech>, devicetree@...r.kernel.org,
sophgo@...ts.linux.dev, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org, Longbin Li <looong.bin@...il.com>
Subject: Re: [PATCH v2 3/4] riscv: dts: sophgo: add reset generator for
Sophgo CV1800 series SoC
On Mon, 2025-06-09 at 07:22 +0800, Inochi Amaoto wrote:
> Add reset generator node for all CV18XX series SoC.
>
> Signed-off-by: Inochi Amaoto <inochiama@...il.com>
Reviewed-by: Alexander Sverdlin <alexander.sverdlin@...il.com>
> ---
> arch/riscv/boot/dts/sophgo/cv180x.dtsi | 7 ++
> arch/riscv/boot/dts/sophgo/cv18xx-reset.h | 98 +++++++++++++++++++++++
> 2 files changed, 105 insertions(+)
> create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-reset.h
--
Alexander Sverdlin.
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