linux-kernel - Re: [PATCH net-next v1 1/3] net: phy: dp83tg720: implement soft reset with asymmetric delay

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Message-ID: <ef433d7f-ff57-4ae4-af27-a005a3080a1d@lunn.ch>
Date: Tue, 10 Jun 2025 15:02:27 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Oleksij Rempel <o.rempel@...gutronix.de>
Cc: Heiner Kallweit <hkallweit1@...il.com>,
	Russell King <linux@...linux.org.uk>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	David Jander <david@...tonic.nl>, kernel@...gutronix.de,
	linux-kernel@...r.kernel.org, netdev@...r.kernel.org
Subject: Re: [PATCH net-next v1 1/3] net: phy: dp83tg720: implement soft
 reset with asymmetric delay

> > > + *
> > > + * 1. Unreliable Link Detection and Synchronized Reset Deadlock
> > > + * ------------------------------------------------------------
> > > + * After a link loss or during link establishment, the DP83TG720 PHY may fail
> > > + * to detect or report link status correctly. To work around this, the PHY must
> > > + * be reset periodically when no link is detected.
> > > + *
> > > + * However, in point-to-point setups where both link partners use the same
> > > + * driver (e.g. Linux on both sides), a synchronized reset pattern may emerge.
> > > + * This leads to a deadlock, where both PHYs reset at the same time and
> > > + * continuously miss each other during auto-negotiation.
> > > + *
> > > + * To address this, the reset procedure includes two components:
> > > + *
> > > + * - A **fixed minimum delay of 1ms** after issuing a hardware reset, as
> > > + *   required by the "DP83TG720S-Q1 1000BASE-T1 Automotive Ethernet PHY with
> > > + *   SGMII and RGMII" datasheet. This ensures MDC access timing is respected
> > > + *   before any further MDIO operations.
> > > + *
> > > + * - An **additional asymmetric delay**, empirically chosen based on
> > > + *   master/slave role. This reduces the risk of synchronized resets on both
> > > + *   link partners. Values are selected to avoid periodic overlap and ensure
> > > + *   the link is re-established within a few cycles.
> > 
> > Maybe there is more about this in the following patches, i've not read
> > them yet. Does autoneg get as far as determining master/slave role? Or
> > are you assuming the link partners are somehow set as
> > prefer_master/prefer_slave?
> 
> This PHY do not support autoneg (as required for automotive PHYs),
> master/slave roles should be assigned by strapping or from software to
> make the link functional.

O.K, please extend the documentation to include this.

If they are incorrectly configured, both have the same role, do they
fail to get a link because of that? So it does not matter they both
have the same delays, it is not going to work whatever...

    Andrew

---
pw-bot: cr