| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID:
<MA0P287MB226219F30F51CC5DA84B4B4CFE6AA@MA0P287MB2262.INDP287.PROD.OUTLOOK.COM>
Date: Tue, 10 Jun 2025 11:14:15 +0800
From: Chen Wang <unicorn_wang@...look.com>
To: Alexander Sverdlin <alexander.sverdlin@...il.com>,
linux-kernel@...r.kernel.org
Cc: Philipp Zabel <p.zabel@...gutronix.de>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Inochi Amaoto <inochiama@...il.com>,
devicetree@...r.kernel.org, sophgo@...ts.linux.dev
Subject: Re: [PATCH 1/2] dt-bindings: reset: sophgo: support SG2000
Hi, Alexander ~
On 2025/6/10 7:04, Alexander Sverdlin wrote:
> Add bindings for the reset module on the Sophgo SG2000 SoC.
>
> Link: https://github.com/sophgo/sophgo-doc/tree/main/SG200X/TRM
> Cc: Chen Wang <unicorn_wang@...look.com>
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@...il.com>
> ---
> .../bindings/reset/sophgo,sg2000-reset.yaml | 35 +++++++
> .../dt-bindings/reset/sophgo,sg2000-reset.h | 92 +++++++++++++++++++
> 2 files changed, 127 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/sophgo,sg2000-reset.yaml
> create mode 100644 include/dt-bindings/reset/sophgo,sg2000-reset.h
>
> diff --git a/Documentation/devicetree/bindings/reset/sophgo,sg2000-reset.yaml b/Documentation/devicetree/bindings/reset/sophgo,sg2000-reset.yaml
> new file mode 100644
> index 000000000000..ab44d45ae061
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/sophgo,sg2000-reset.yaml
Need not a new reset binding for sg2000, you can reuse existing
sophgo,sg2042-reset.yaml.
> @@ -0,0 +1,35 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reset/sophgo,sg2000-reset.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Sophgo SG2000 SoC Reset Controller
> +
> +maintainers:
> + - Chen Wang <unicorn_wang@...look.com>
Use your contact info if really need this file.
In fact, I think your patch can be combined with another patch [1].
Because SG2000/SG2002 are actually developed from CV18XX, their reset IP
is almost the same.
Link:
https://lore.kernel.org/linux-riscv/20250608232214.771855-1-inochiama@gmail.com/
[1]
Can you talk with Inochi on this?
> +
> +properties:
> + compatible:
> + const: sophgo,sg2000-reset
> +
> + reg:
> + maxItems: 1
> +
> + "#reset-cells":
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - "#reset-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + rstgen: reset-controller@...3000 {
> + compatible = "sophgo,sg2000-reset";
> + reg = <0x3003000 0x28>;
> + #reset-cells = <1>;
> + };
> diff --git a/include/dt-bindings/reset/sophgo,sg2000-reset.h b/include/dt-bindings/reset/sophgo,sg2000-reset.h
> new file mode 100644
> index 000000000000..23604a800f66
> --- /dev/null
> +++ b/include/dt-bindings/reset/sophgo,sg2000-reset.h
> @@ -0,0 +1,92 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> +
> +#ifndef __DT_BINDINGS_RESET_SOPHGO_SG2000_H_
> +#define __DT_BINDINGS_RESET_SOPHGO_SG2000_H_
> +
> +#define RST_DDR 2
> +#define RST_H264C 3
> +#define RST_JPEG 4
> +#define RST_H265C 5
> +#define RST_VIPSYS 6
> +#define RST_TDMA 7
> +#define RST_TPU 8
> +#define RST_TPUSYS 9
> +#define RST_USB 11
> +#define RST_ETH0 12
> +#define RST_ETH1 13
> +#define RST_NAND 14
> +#define RST_EMMC 15
> +#define RST_SD0 16
> +#define RST_SDMA 18
> +#define RST_I2S0 19
> +#define RST_I2S1 20
> +#define RST_I2S2 21
> +#define RST_I2S3 22
> +#define RST_UART0 23
> +#define RST_UART1 24
> +#define RST_UART2 25
> +#define RST_UART3 26
> +#define RST_I2C0 27
> +#define RST_I2C1 28
> +#define RST_I2C2 29
> +#define RST_I2C3 30
> +#define RST_I2C4 31
> +
> +#define RST_PWM0 32
> +#define RST_PWM1 33
> +#define RST_PWM2 34
> +#define RST_PWM3 35
> +#define RST_SPI0 40
> +#define RST_SPI1 41
> +#define RST_SPI2 42
> +#define RST_SPI3 43
> +#define RST_GPIO0 44
> +#define RST_GPIO1 45
> +#define RST_GPIO2 46
> +#define RST_EFUSE 47
> +#define RST_WDT 48
> +#define RST_AHB_ROM 49
> +#define RST_SPIC 50
> +#define RST_TEMPSEN 51
> +#define RST_SARADC 52
> +#define RST_COMBO_PHY0 58
> +#define RST_SPI_NAND 61
> +#define RST_SE 62
> +
> +#define RST_UART4 74
> +#define RST_GPIO3 75
> +#define RST_SYSTEM 76
> +#define RST_TIMER 77
> +#define RST_TIMER0 78
> +#define RST_TIMER1 79
> +#define RST_TIMER2 80
> +#define RST_TIMER3 81
> +#define RST_TIMER4 82
> +#define RST_TIMER5 83
> +#define RST_TIMER6 84
> +#define RST_TIMER7 85
> +#define RST_WGN0 86
> +#define RST_WGN1 87
> +#define RST_WGN2 88
> +#define RST_KEYSCAN 89
> +#define RST_AUDDAC 91
> +#define RST_AUDDAC_APB 92
> +#define RST_AUDADC 93
> +#define RST_VCSYS 95
> +
> +#define RST_ETHPHY 96
> +#define RST_ETHPHY_APB 97
> +#define RST_AUDSRC 98
> +#define RST_VIP_CAM0 99
> +#define RST_WDT1 100
> +#define RST_WDT2 101
> +
> +#define RST_CPUCORE0 1152
> +#define RST_CPUCORE1 1153
> +#define RST_CPUCORE2 1154
> +#define RST_CPUCORE3 1155
> +#define RST_CPUSYS0 1156
> +#define RST_CPUSYS1 1157
> +#define RST_CPUSYS2 1158
> +
> +#endif /* __DT_BINDINGS_RESET_SOPHGO_SG2000_H_ */
Powered by blists - more mailing lists