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Message-ID: <2a1b81d3-ec5f-4cbb-9660-899648ab4538@huawei.com>
Date: Tue, 10 Jun 2025 21:30:01 +0800
From: Yongbang Shi <shiyongbang@...wei.com>
To: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
CC: <xinliang.liu@...aro.org>, <tiantao6@...ilicon.com>,
	<maarten.lankhorst@...ux.intel.com>, <mripard@...nel.org>,
	<tzimmermann@...e.de>, <airlied@...il.com>, <daniel@...ll.ch>,
	<kong.kongxinwei@...ilicon.com>, <liangjian010@...wei.com>,
	<chenjianmin@...wei.com>, <lidongming5@...wei.com>, <libaihan@...wei.com>,
	<shenjian15@...wei.com>, <shaojijie@...wei.com>,
	<jani.nikula@...ux.intel.com>, <dri-devel@...ts.freedesktop.org>,
	<linux-kernel@...r.kernel.org>, <shiyongbang@...wei.com>
Subject: Re: [PATCH drm-dp 07/10] drm/hisilicon/hibmc: add dp encoder modeset


> On Fri, May 30, 2025 at 05:54:29PM +0800, Yongbang Shi wrote:
>> From: Baihan Li <libaihan@...wei.com>
>>
>> Add GPU display control enable in dp_mode_set(), which is already
>> in vdac's mode_set, however, if vdac is not connected, GPU
>> cannot work.
>>
>> Fixes: f9698f802e50 ("drm/hisilicon/hibmc: Restructuring the header dp_reg.h")
> Typically, incorrect tag.
>
>> Signed-off-by: Baihan Li <libaihan@...wei.com>
>> ---
>>   drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c | 18 ++++++++++++++++++
>>   1 file changed, 18 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c
>> index e4b13f21ccb3..d9ae7567ebb7 100644
>> --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c
>> +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c
>> @@ -11,6 +11,7 @@
>>   #include <drm/drm_edid.h>
>>   
>>   #include "hibmc_drm_drv.h"
>> +#include "hibmc_drm_regs.h"
>>   #include "dp/dp_hw.h"
>>   
>>   #define HIBMC_DP_MASKED_SINK_HPD_PLUG_INT	BIT(2)
>> @@ -169,9 +170,26 @@ static void hibmc_dp_encoder_disable(struct drm_encoder *drm_encoder,
>>   	hibmc_dp_display_en(dp, false);
>>   }
>>   
>> +static void hibmc_dp_encoder_mode_set(struct drm_encoder *encoder,
>> +				      struct drm_crtc_state *crtc_state,
>> +				      struct drm_connector_state *conn_state)
>> +{
>> +	struct drm_device *dev = encoder->dev;
>> +	struct hibmc_drm_private *priv = to_hibmc_drm_private(dev);
>> +	u32 reg;
>> +
>> +	reg = readl(priv->mmio + HIBMC_DISPLAY_CONTROL_HISILE);
>> +	reg |= HIBMC_DISPLAY_CONTROL_FPVDDEN(1);
>> +	reg |= HIBMC_DISPLAY_CONTROL_PANELDATE(1);
>> +	reg |= HIBMC_DISPLAY_CONTROL_FPEN(1);
>> +	reg |= HIBMC_DISPLAY_CONTROL_VBIASEN(1);
>> +	writel(reg, priv->mmio + HIBMC_DISPLAY_CONTROL_HISILE);
> This is a c&p of the corresponding VDAC code. Please move it to a common
> function instead.
>
> BTW: what does it mean that the GPU cannot work? Do you mean that the
> display hardware doesn't work or that the GL calls do not work?

Okay, I will delete it here.

It's about hardware, which may cause no signal.


>> +}
>> +
>>   static const struct drm_encoder_helper_funcs hibmc_dp_encoder_helper_funcs = {
>>   	.atomic_enable = hibmc_dp_encoder_enable,
>>   	.atomic_disable = hibmc_dp_encoder_disable,
>> +	.atomic_mode_set = hibmc_dp_encoder_mode_set,
>>   };
>>   
>>   irqreturn_t hibmc_dp_hpd_isr(int irq, void *arg)
>> -- 
>> 2.33.0
>>

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