linux-kernel - RE: [Intel-wired-lan] [PATCH net-next v4 1/3] dpll: add reference-sync netlink attribute

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <SJ2PR11MB8452C09EFD87AAE4CE9A44819B6AA@SJ2PR11MB8452.namprd11.prod.outlook.com>
Date: Tue, 10 Jun 2025 03:49:03 +0000
From: "Kubalewski, Arkadiusz" <arkadiusz.kubalewski@...el.com>
To: Jakub Kicinski <kuba@...nel.org>
CC: "donald.hunter@...il.com" <donald.hunter@...il.com>, "davem@...emloft.net"
	<davem@...emloft.net>, "edumazet@...gle.com" <edumazet@...gle.com>,
	"pabeni@...hat.com" <pabeni@...hat.com>, "horms@...nel.org"
	<horms@...nel.org>, "vadim.fedorenko@...ux.dev" <vadim.fedorenko@...ux.dev>,
	"jiri@...nulli.us" <jiri@...nulli.us>, "Nguyen, Anthony L"
	<anthony.l.nguyen@...el.com>, "Kitszel, Przemyslaw"
	<przemyslaw.kitszel@...el.com>, "andrew+netdev@...n.ch"
	<andrew+netdev@...n.ch>, "Loktionov, Aleksandr"
	<aleksandr.loktionov@...el.com>, "corbet@....net" <corbet@....net>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"intel-wired-lan@...ts.osuosl.org" <intel-wired-lan@...ts.osuosl.org>,
	"linux-rdma@...r.kernel.org" <linux-rdma@...r.kernel.org>,
	"linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>, "Olech, Milena"
	<milena.olech@...el.com>
Subject: RE: [Intel-wired-lan] [PATCH net-next v4 1/3] dpll: add
 reference-sync netlink attribute

>From: Intel-wired-lan <intel-wired-lan-bounces@...osl.org> On Behalf Of
>Jakub Kicinski
>Sent: Friday, May 30, 2025 2:49 AM
>
>On Fri, 23 May 2025 19:26:48 +0200 Arkadiusz Kubalewski wrote:
>> +The device may support the Reference SYNC feature, which allows the
>>combination
>> +of two inputs into a Reference SYNC pair. In this configuration, clock
>>signals
>> +from both inputs are used to synchronize the dpll device. The higher
>>frequency
>> +signal is utilized for the loop bandwidth of the DPLL, while the lower
>>frequency
>> +signal is used to syntonize the output signal of the DPLL device. This
>>feature
>> +enables the provision of a high-quality loop bandwidth signal from an
>>external
>> +source.
>
>I'm uninitiated into the deeper arts of time sync, but to me this
>sounds like a reference clock. Are you trying not to call it clock
>because in time clock means a ticker, and this is an oscillator?
>

We shall refer to a reference clock for each input pin, right?
TBH, I have reused the name from dpll chip docs, I believe they have
tried to make similar features and naming convention for both:
Embedded SYNC/Reference SYNC, and that makes some sense.

>> +A capable input provides a list of inputs that can be paired to create a
>> +Reference SYNC pair. To control this feature, the user must request a
>>desired
>> +state for a target pin: use ``DPLL_PIN_STATE_CONNECTED`` to enable or
>> +``DPLL_PIN_STATE_DISCONNECTED`` to disable the feature. Only two pins
>>can be
>> +bound to form a Reference SYNC pair at any given time.
>
>Mostly I got confused by the doc saying "Reference SYNC pair".
>I was expecting that you'll have to provide 2 ref sync signals.
>But IIUC the first signal is still the existing signal we lock
>into, so the pair is of a reference sync + an input pin?
>Not a pair of two reference syncs.
>
>IOW my reading of the doc made me expect 2 pins to always be passed in
>as ref sync, but the example from the cover letter shows only adding
>one.

Yes, exactly, will try to improve this in next version.

Thank you!
Arkadiusz