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Message-ID: <20250610-loose-quick-robin-e2ceae@houat>
Date: Tue, 10 Jun 2025 17:39:12 +0200
From: Maxime Ripard <mripard@...nel.org>
To: Brian Masney <bmasney@...hat.com>
Cc: Stephen Boyd <sboyd@...nel.org>, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, Arnd Bergmann <arnd@...db.de>,
Thomas Gleixner <tglx@...utronix.de>, Michael Turquette <mturquette@...libre.com>,
Alberto Ruiz <aruiz@...hat.com>
Subject: Re: [PATCH v2 05/10] clk: test: introduce test suite for sibling
rate changes on a divider
Hi,
On Wed, May 28, 2025 at 07:16:51PM -0400, Brian Masney wrote:
> Introduce a test suite that creates a parent with two divider-only
> children, and ensure that changing the rate of one child does not
> affect the rate of the sibling.
>
> Some of the tests are disabled until the relevant issue(s) are fixed in
> the clk core.
>
> Signed-off-by: Brian Masney <bmasney@...hat.com>
> ---
> drivers/clk/clk_test.c | 139 +++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 139 insertions(+)
>
> diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c
> index 4908fb9c0c46e34063ecf696e49b48510da44538..35f516fd71a2e33ca19a0512bd2db02111ea644c 100644
> --- a/drivers/clk/clk_test.c
> +++ b/drivers/clk/clk_test.c
> @@ -653,6 +653,144 @@ clk_multiple_parents_mux_test_suite = {
> .test_cases = clk_multiple_parents_mux_test_cases,
> };
>
> +struct clk_rate_change_sibling_div_div_context {
> + struct clk_dummy_context parent;
> + struct clk_dummy_div child1, child2;
> + struct clk *parent_clk, *child1_clk, *child2_clk;
> +};
> +
> +static int clk_rate_change_sibling_div_div_test_init(struct kunit *test)
> +{
> + struct clk_rate_change_sibling_div_div_context *ctx;
> + int ret;
> +
> + ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
> + if (!ctx)
> + return -ENOMEM;
> + test->priv = ctx;
> +
> + ctx->parent.hw.init = CLK_HW_INIT_NO_PARENT("parent", &clk_dummy_rate_ops, 0);
> + ctx->parent.rate = DUMMY_CLOCK_RATE_24_MHZ;
> + ret = clk_hw_register_kunit(test, NULL, &ctx->parent.hw);
> + if (ret)
> + return ret;
> +
> + ctx->child1.hw.init = CLK_HW_INIT_HW("child1", &ctx->parent.hw,
> + &clk_dummy_div_ops,
> + CLK_SET_RATE_PARENT);
> + ret = clk_hw_register_kunit(test, NULL, &ctx->child1.hw);
> + if (ret)
> + return ret;
> +
> + ctx->child2.hw.init = CLK_HW_INIT_HW("child2", &ctx->parent.hw,
> + &clk_dummy_div_ops,
> + CLK_SET_RATE_PARENT);
> + ret = clk_hw_register_kunit(test, NULL, &ctx->child2.hw);
> + if (ret)
> + return ret;
> +
> + ctx->parent_clk = clk_hw_get_clk(&ctx->parent.hw, NULL);
> + ctx->child1_clk = clk_hw_get_clk(&ctx->child1.hw, NULL);
> + ctx->child2_clk = clk_hw_get_clk(&ctx->child2.hw, NULL);
> +
> + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->parent_clk), DUMMY_CLOCK_RATE_24_MHZ);
> +
> + return 0;
> +}
We should probably document that we're using CLK_SET_RATE_PARENT on the
dividers, because it'll affect the outcome of the tests.
The rest looks good to me, but is still dependant on some earlier
discussions being solved.
Maxime
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