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Message-ID: <cover.1749588810.git.geraldogabriel@gmail.com> Date: Tue, 10 Jun 2025 18:19:35 -0300 From: Geraldo Nascimento <geraldogabriel@...il.com> To: linux-rockchip@...ts.infradead.org Cc: Shawn Lin <shawn.lin@...k-chips.com>, Lorenzo Pieralisi <lpieralisi@...nel.org>, Krzysztof WilczyĆski <kw@...ux.com>, Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>, Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>, Heiko Stuebner <heiko@...ech.de>, Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>, linux-phy@...ts.infradead.org, linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org Subject: [RFC PATCH v2 0/4] Quality Improvements for Rockchip-IP PCIe During a 30-day debugging-run fighting quirky PCIe devices on RK3399 some quality improvements began to take form and this is my attempt at upstreaming it. It will ensure maximum chance of retraining to Gen2 5.0GT/s, on all four lanes and plus if anybody is debugging the PHY they'll now get real values from TEST_I[3:0] for every TEST_ADDR[4:0] without risk of locking up kernel like with present broken async strobe TEST_WRITE. --- V1 -> V2: use standard PCIe defines as suggested by Bjorn Geraldo Nascimento (4): PCI: pcie-rockchip: add Link Control and Status Register 2 PCI: rockchip-host: Set Target Link Speed before retraining phy: rockchip-pcie: enable all four lanes phy: rockchip-pcie: adjust read mask and write strobe disable drivers/pci/controller/pcie-rockchip-host.c | 4 ++++ drivers/pci/controller/pcie-rockchip.h | 10 ++++++---- drivers/phy/rockchip/phy-rockchip-pcie.c | 16 +++++++++------- 3 files changed, 19 insertions(+), 11 deletions(-) -- 2.49.0
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