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Message-ID: <g3wzmewsjrbeteumfv3ibqwj62cwm45whledqez4issjkmqao3@oymrmm57c7bx>
Date: Tue, 10 Jun 2025 09:58:20 +0800
From: Inochi Amaoto <inochiama@...il.com>
To: Alexander Sverdlin <alexander.sverdlin@...il.com>,
sophgo@...ts.linux.dev, soc@...ts.linux.dev
Cc: Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Chen Wang <unicorn_wang@...look.com>, Inochi Amaoto <inochiama@...il.com>,
Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>,
Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org>, Arnd Bergmann <arnd@...db.de>,
Jisheng Zhang <jszhang@...nel.org>, Haylen Chu <heylenay@...look.com>,
Chao Wei <chao.wei@...hgo.com>, devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v6 2/6] arm64: dts: sophgo: Add initial SG2000 SoC device
tree
On Tue, Jun 10, 2025 at 01:41:13AM +0200, Alexander Sverdlin wrote:
> Add initial device tree for the SG2000 SoC by SOPHGO (from ARM64 PoV).
>
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@...il.com>
> ---
> arch/arm64/boot/dts/sophgo/sg2000.dtsi | 91 ++++++++++++++++++++++++++
> 1 file changed, 91 insertions(+)
> create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi
>
> diff --git a/arch/arm64/boot/dts/sophgo/sg2000.dtsi b/arch/arm64/boot/dts/sophgo/sg2000.dtsi
> new file mode 100644
> index 000000000000..5e69ccfbab56
> --- /dev/null
> +++ b/arch/arm64/boot/dts/sophgo/sg2000.dtsi
> @@ -0,0 +1,92 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +
> +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI (nr)
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <riscv/sophgo/cv180x.dtsi>
> +#include <riscv/sophgo/cv181x.dtsi>
> +
> +/ {
> + compatible = "sophgo,sg2000";
> + interrupt-parent = <&gic>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + reg = <0>;
> + enable-method = "psci";
> + i-cache-size = <32768>;
> + d-cache-size = <32768>;
> + next-level-cache = <&l2>;
> + };
> +
> + l2: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + cache-unified;
> + cache-size = <0x20000>;
> + };
> + };
> +
> + memory@...00000 {
> + device_type = "memory";
> + reg = <0x80000000 0x20000000>; /* 512MiB */
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + cpu_on = <0xc4000003>;
> + cpu_off = <0x84000002>;
> + };
> +
> + soc {
> + gic: interrupt-controller@...1000 {
> + compatible = "arm,cortex-a15-gic";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + reg = <0x01f01000 0x1000>,
> + <0x01f02000 0x2000>;
> + };
> +
> + pinctrl: pinctrl@...1000 {
> + compatible = "sophgo,sg2000-pinctrl";
> + reg = <0x03001000 0x1000>,
> + <0x05027000 0x1000>;
> + reg-names = "sys", "rtc";
> + };
> +
> + clk: clock-controller@...2000 {
> + compatible = "sophgo,sg2000-clk";
> + reg = <0x03002000 0x1000>;
> + clocks = <&osc>;
> + #clock-cells = <1>;
> + };
> +
> + rst: reset-controller@...3000 {
> + compatible = "sophgo,sg2000-reset";
> + reg = <0x03003000 0x28>;
> + #reset-cells = <1>;
> + };
Remove this and use common cv1800b-reset.
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
> + always-on;
> + clock-frequency = <25000000>;
> + };
> +};
> --
> 2.49.0
>
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