linux-kernel - Re: [PATCH v1 3/7] dt-bindings: interrupt-controller: add generic Risc-v aclint-sswi

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Message-ID:
 <AS2PR09MB6296534EB4110B806DE700A6946AA@AS2PR09MB6296.eurprd09.prod.outlook.com>
Date: Tue, 10 Jun 2025 09:55:00 +0000
From: Vladimir Kondratiev <Vladimir.Kondratiev@...ileye.com>
To: Conor Dooley <conor@...nel.org>
CC: Thomas Gleixner <tglx@...utronix.de>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
	Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt
	<palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti
	<alex@...ti.fr>, Anup Patel <anup@...infault.org>, Chen Wang
	<unicorn_wang@...look.com>, Inochi Amaoto <inochiama@...il.com>, Sunil V L
	<sunilvl@...tanamicro.com>, "Rafael J . Wysocki"
	<rafael.j.wysocki@...el.com>, Ryo Takakura <takakura@...inux.co.jp>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
	"sophgo@...ts.linux.dev" <sophgo@...ts.linux.dev>
Subject: Re: [PATCH v1 3/7] dt-bindings: interrupt-controller: add generic
 Risc-v aclint-sswi

>> Link: https://github.com/riscvarchive/riscv-aclint [1]
>What is the ratification status of this spec?

This spec is in a "draft" state, and perspective for its ratification is unclear.
So I understand I can't use "riscv," prefixes, I will convert it to adding
platform-specific variant of the SSWI, and submit v2.

>s/Risc-V/RISC-V/g

Yes sure

>> +    oneOf:
>> +      - items:
>> +          - enum:
>> +              - sophgo,sg2044-aclint-sswi
>> +          - const: thead,c900-aclint-sswi
>> +      - items:
>> +          - const: riscv,aclint-sswi
>You need a specific compatible for your implementation.

Yes, doing this

>Whether or not this compatible is viable depends on the answer to the
>ratification status and/or plan for the spec.

Replacing "riscv," compatible with platform-specific one

>> +  interrupts-extended:
>> +    minItems: 1
>> +    maxItems: 4095
>> +
>> +  riscv,hart-indexes:
>> +    $ref: /schemas/types.yaml#/definitions/uint32-array
>> +    minItems: 1
>> +    maxItems: 16384
>maxItems is 4x what is allowed for interrupts-extended. Why?

Fixing this. It was copied from the dt-bindings for the APLIC where
maxItems for "interrupts-extended" specified as 16384

>Please constrain this property to only be permitted on !thead.

Doing this

>> +      riscv,hart-indexes = <0 1 0x10 0x11>;
>Please be consistent. Hex or decimal, but not both.

Sure

Thanks, Vladimir