linux-kernel - Re: [PATCH net-next v1 1/3] net: phy: dp83tg720: implement soft reset with asymmetric delay

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Message-ID: <534b3aed-bef5-410e-b970-495b62534d96@lunn.ch>
Date: Tue, 10 Jun 2025 14:16:39 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Oleksij Rempel <o.rempel@...gutronix.de>
Cc: Heiner Kallweit <hkallweit1@...il.com>,
	Russell King <linux@...linux.org.uk>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	David Jander <david@...tonic.nl>, kernel@...gutronix.de,
	linux-kernel@...r.kernel.org, netdev@...r.kernel.org
Subject: Re: [PATCH net-next v1 1/3] net: phy: dp83tg720: implement soft
 reset with asymmetric delay

On Tue, Jun 10, 2025 at 10:10:57AM +0200, Oleksij Rempel wrote:
> From: David Jander <david@...tonic.nl>
> 
> Add a .soft_reset callback for the DP83TG720 PHY that issues a hardware
> reset followed by an asymmetric post-reset delay. The delay differs
> based on the PHY's master/slave role to avoid synchronized reset
> deadlocks, which are known to occur when both link partners use
> identical reset intervals.
> 
> The delay includes:
> - a fixed 1ms wait to satisfy MDC access timing per datasheet, and
> - an empirically chosen extra delay (97ms for master, 149ms for slave).
> 
> Co-developed-by: Oleksij Rempel <o.rempel@...gutronix.de>
> Signed-off-by: Oleksij Rempel <o.rempel@...gutronix.de>
> Signed-off-by: David Jander <david@...tonic.nl>

Hi Oleksij

Since you are submitting it, your Signed-off-by should come last. The
order signifies the developers who passed it along towards merging.

> ---
>  drivers/net/phy/dp83tg720.c | 75 ++++++++++++++++++++++++++++++++-----
>  1 file changed, 65 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/net/phy/dp83tg720.c b/drivers/net/phy/dp83tg720.c
> index 7e76323409c4..2c86d05bf857 100644
> --- a/drivers/net/phy/dp83tg720.c
> +++ b/drivers/net/phy/dp83tg720.c
> @@ -12,6 +12,42 @@
>  
>  #include "open_alliance_helpers.h"
>  
> +/*
> + * DP83TG720 PHY Limitations and Workarounds
> + *
> + * The DP83TG720 1000BASE-T1 PHY has several limitations that require
> + * software-side mitigations. These workarounds are implemented throughout
> + * this driver. This section documents the known issues and their corresponding
> + * mitigation strategies.

Is there a public errata you can reference?

> + *
> + * 1. Unreliable Link Detection and Synchronized Reset Deadlock
> + * ------------------------------------------------------------
> + * After a link loss or during link establishment, the DP83TG720 PHY may fail
> + * to detect or report link status correctly. To work around this, the PHY must
> + * be reset periodically when no link is detected.
> + *
> + * However, in point-to-point setups where both link partners use the same
> + * driver (e.g. Linux on both sides), a synchronized reset pattern may emerge.
> + * This leads to a deadlock, where both PHYs reset at the same time and
> + * continuously miss each other during auto-negotiation.
> + *
> + * To address this, the reset procedure includes two components:
> + *
> + * - A **fixed minimum delay of 1ms** after issuing a hardware reset, as
> + *   required by the "DP83TG720S-Q1 1000BASE-T1 Automotive Ethernet PHY with
> + *   SGMII and RGMII" datasheet. This ensures MDC access timing is respected
> + *   before any further MDIO operations.
> + *
> + * - An **additional asymmetric delay**, empirically chosen based on
> + *   master/slave role. This reduces the risk of synchronized resets on both
> + *   link partners. Values are selected to avoid periodic overlap and ensure
> + *   the link is re-established within a few cycles.

Maybe there is more about this in the following patches, i've not read
them yet. Does autoneg get as far as determining master/slave role? Or
are you assuming the link partners are somehow set as
prefer_master/prefer_slave?

	Andrew