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Message-ID: <aEnDHerp45syb8iO@e129823.arm.com>
Date: Wed, 11 Jun 2025 18:55:41 +0100
From: Yeoreum Yun <yeoreum.yun@....com>
To: Marc Zyngier <maz@...nel.org>
Cc: catalin.marinas@....com, will@...nel.org, broonie@...nel.org,
oliver.upton@...ux.dev, ardb@...nel.org, frederic@...nel.org,
james.morse@....com, joey.gouly@....com,
scott@...amperecomputing.com, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/6] arm64: cpufeature: add FEAT_LSUI
Hi Marc,
> On Wed, 11 Jun 2025 11:49:11 +0100,
> Yeoreum Yun <yeoreum.yun@....com> wrote:
> >
> > Since Armv9.6, FEAT_LSUI supplies load/store instructions
> > for privileged level to access user memory without clearing PSTATE.PAN bit.
> >
> > Add LSUI feature so that the unprevilieged load/store instrcutions
>
> nit: instructions
Thanks.
> > could be used when kernel accesses user memory without clearing PSTATE.PAN bit.
> >
> > Signed-off-by: Yeoreum Yun <yeoreum.yun@....com>
> > ---
> > arch/arm64/kernel/cpufeature.c | 8 ++++++++
> > arch/arm64/tools/cpucaps | 1 +
> > 2 files changed, 9 insertions(+)
> >
> > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> > index b34044e20128..d914982c7cee 100644
> > --- a/arch/arm64/kernel/cpufeature.c
> > +++ b/arch/arm64/kernel/cpufeature.c
> > @@ -278,6 +278,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
> >
> > static const struct arm64_ftr_bits ftr_id_aa64isar3[] = {
> > ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0),
> > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_LSUI_SHIFT, 4, ID_AA64ISAR3_EL1_LSUI_NI),
> > ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0),
> > ARM64_FTR_END,
> > };
>
> Please enable the equivalent bits in KVM so that the feature can be
> exposed to a guest.
Okay. I'll add in next round.
Thanks!
--
Sincerely,
Yeoreum Yun
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